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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [sw/] [zasm/] [test.S] - Diff between revs 36 and 39
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| Rev 36 |
Rev 39 |
| Line 517... |
Line 517... |
cmp r0,r1
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cmp r0,r1
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trap.ne r11
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trap.ne r11
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cmp r0,r7
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cmp r0,r7
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trap.ne r11
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trap.ne r11
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#endif
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#endif
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#define PIPELINE_STACK_TEST
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#ifdef PIPELINE_STACK_TEST
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ldi $0x0f000,r11 // Mark our test
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LDI 1,R0
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MOV 1(R0),R1
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MOV 1(R1),R2
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MOV 1(R2),R3
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MOV 1(R3),R4
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MOV 1(R4),R5
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MOV 1(R5),R6
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JSR(pipeline_stack_test,R7)
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CMP 1,R0
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trap.ne R11
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CMP 2,R1
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trap.ne R11
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CMP 3,R2
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trap.ne R11
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CMP 4,R3
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trap.ne R11
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CMP 5,R4
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trap.ne R11
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CMP 6,R5
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trap.ne R11
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CMP 7,R6
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trap.ne R11
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#endif
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// Return success / Test the trap interrupt
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// Return success / Test the trap interrupt
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clr r11
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clr r11
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trap r11
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trap r11
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noop
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noop
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noop
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noop
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| Line 546... |
Line 573... |
MOV R2,R0
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MOV R2,R0
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POP(R2,SP)
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POP(R2,SP)
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POP(R1,SP)
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POP(R1,SP)
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RET
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RET
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#endif
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#endif
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#ifdef PIPELINE_STACK_TEST
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pipeline_stack_test:
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SUB 13,SP
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STO R0,1(SP)
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STO R1,2(SP)
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STO R2,3(SP)
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STO R3,4(SP)
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STO R4,5(SP)
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STO R5,6(SP)
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STO R6,7(SP)
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STO R7,8(SP)
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STO R8,9(SP)
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STO R9,10(SP)
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STO R10,11(SP)
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STO R11,12(SP)
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STO R12,13(SP)
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XOR -1,R0
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XOR -1,R1
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XOR -1,R2
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XOR -1,R3
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XOR -1,R4
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XOR -1,R5
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XOR -1,R6
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XOR -1,R7
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XOR -1,R8
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XOR -1,R9
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XOR -1,R10
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XOR -1,R11
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XOR -1,R12
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LOD 1(SP),R0
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LOD 2(SP),R1
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LOD 3(SP),R2
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LOD 4(SP),R3
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LOD 5(SP),R4
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LOD 6(SP),R5
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LOD 7(SP),R6
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LOD 8(SP),R7
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LOD 9(SP),R8
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LOD 10(SP),R9
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LOD 11(SP),R10
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LOD 12(SP),R11
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LOD 13(SP),R12
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ADD 13,SP
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LOD 1(SP),PC
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#endif // PIPELINE_STACK_TEST
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fill 512,0
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fill 512,0
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stack: // Must point to a valid word initially
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stack: // Must point to a valid word initially
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word 0
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word 0
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