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[/] [zipcpu/] [trunk/] [sw/] [zasm/] [test.S] - Diff between revs 39 and 46

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Rev 39 Rev 46
Line 82... Line 82...
#define LOOP_TEST
#define LOOP_TEST
#define SHIFT_TEST
#define SHIFT_TEST
#define TRAP_TEST
#define TRAP_TEST
#define MPY_TEST
#define MPY_TEST
#define PUSH_TEST
#define PUSH_TEST
 
#define PIPELINE_STACK_TEST
 
#define MEM_PIPELINE_TEST
test:
test:
#ifdef  DO_TEST_ASSEMBLER
#ifdef  DO_TEST_ASSEMBLER
; We start out by testing our assembler.  We give it some instructions, which
; We start out by testing our assembler.  We give it some instructions, which
; are then manually checked  by disassembling/dumping the result and making
; are then manually checked  by disassembling/dumping the result and making
; certain they match.  This is not an automated test, but it is an important
; certain they match.  This is not an automated test, but it is an important
Line 518... Line 520...
        trap.ne r11
        trap.ne r11
        cmp     r0,r7
        cmp     r0,r7
        trap.ne r11
        trap.ne r11
#endif
#endif
 
 
#define PIPELINE_STACK_TEST
 
#ifdef  PIPELINE_STACK_TEST
#ifdef  PIPELINE_STACK_TEST
        ldi     $0x0f000,r11    // Mark our test
        ldi     $0x0f000,r11    // Mark our test
        LDI     1,R0
        LDI     1,R0
        MOV     1(R0),R1
        MOV     1(R0),R1
        MOV     1(R1),R2
        MOV     1(R1),R2
Line 544... Line 545...
        CMP     6,R5
        CMP     6,R5
        trap.ne R11
        trap.ne R11
        CMP     7,R6
        CMP     7,R6
        trap.ne R11
        trap.ne R11
#endif
#endif
 
 
 
#ifdef  MEM_PIPELINE_TEST
 
        JSR(mem_pipeline_test,R0)
 
#endif  // MEM_PIPELINE_TEST
 
 
// Return success / Test the trap interrupt
// Return success / Test the trap interrupt
        clr     r11
        clr     r11
        trap    r11
        trap    r11
        noop
        noop
        noop
        noop
Line 620... Line 626...
        LOD     13(SP),R12
        LOD     13(SP),R12
        ADD     13,SP
        ADD     13,SP
        LOD     1(SP),PC
        LOD     1(SP),PC
#endif // PIPELINE_STACK_TEST
#endif // PIPELINE_STACK_TEST
 
 
 
#ifdef  MEM_PIPELINE_TEST
 
mem_pipeline_test:
 
        SUB     4,SP
 
        STO     R0,1(SP)
 
        STO     R1,2(SP)
 
        LDI     0x10000,R11
 
        ;
 
        ; Test #1 ... Let's start by writing a value to memory
 
        LDI     -1,R0
 
        CLR     R1
 
        STO     R0,3(SP)
 
        LOD     3(SP),R1
 
        CMP     R1,R0
 
        MOV.NZ  R11,CC
 
 
 
        ; Test #2, reading and then writing a value from memory
 
        NOP
 
        NOP
 
        CLR     R0
 
        CLR     R1
 
        LOD     3(SP),R0        ; This should load back up our -1 value
 
        STO     R0,4(SP)
 
        ; Insist that the pipeline clear
 
        LOD     3(SP),R0
 
        ; Now let's try loading into R1
 
        NOP
 
        NOP
 
        NOP
 
        NOP
 
        LOD     4(SP),R1
 
        CMP     R1,R0
 
        MOV.NZ  R11,CC
 
 
 
        LOD     1(SP),R0
 
        LOD     2(SP),R1
 
        ADD     4,SP
 
        RETN
 
#endif
 
 
        fill    512,0
        fill    512,0
stack:  // Must point to a valid word initially
stack:  // Must point to a valid word initially
        word    0
        word    0

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