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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: devbus.h
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// Filename: devbus.h
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//
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//
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// Project: UART to WISHBONE FPGA library
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// Project: UART to WISHBONE FPGA library
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//
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//
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// Purpose: The purpose of this file is to document an interface which
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// Purpose: The purpose of this file is to document an interface which
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// any devic with a bus, whether it be implemented over a UART,
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// any device with a bus, whether it be implemented over a UART,
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// an ethernet, or a PCI express bus, must implement. This
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// an ethernet, or a PCI express bus, must implement. This describes
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// describes only an interface, and not how that interface is
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// only an interface, and not how that interface is to be accomplished.
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// to be accomplished.
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//
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// The neat part of this interface is that, if programs are designed to
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// work with it, than the implementation details may be changed later
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// and any program that once worked with the interface should be able
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// to continue to do so. (i.e., switch from a UART controlled bus to a
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// PCI express controlled bus, with minimal change to the software of
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// interest.)
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//
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//
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// Creator: Dan Gisselquist
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Technology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015-2016, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#ifndef DEVBUS_H
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#ifndef DEVBUS_H
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#define DEVBUS_H
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#define DEVBUS_H
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virtual void kill(void) = 0;
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virtual void kill(void) = 0;
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virtual void close(void) = 0;
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virtual void close(void) = 0;
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// Write a single value to a single address
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// Write a single value to a single address
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// a is the address of the value to be read as it exists on the
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// wishbone bus within the FPGA.
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// v is the singular value to write to this address
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virtual void writeio(const BUSW a, const BUSW v) = 0;
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virtual void writeio(const BUSW a, const BUSW v) = 0;
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// Read a single value to a single address
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// Read a single value to a single address
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// a is the address of the value to be read as it exists on the
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// wishbone bus within the FPGA.
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// This function returns the value read from the device wishbone
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// at address a.
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virtual BUSW readio(const BUSW a) = 0;
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virtual BUSW readio(const BUSW a) = 0;
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// Read a series of values from values from a block of memory
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// Read a series of values from values from a block of memory
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// a is the address of the value to be read as it exists on the
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// wishbone bus within the FPGA.
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// len is the number of words to read
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// buf is a pointer to a place to store the words once read.
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// This is equivalent to:
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// for(int i=0; i<len; i++)
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// buf[i] = readio(a+i);
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// only it's faster in our implementation.
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virtual void readi(const BUSW a, const int len, BUSW *buf) = 0;
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virtual void readi(const BUSW a, const int len, BUSW *buf) = 0;
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// Read a series of values from the same address in memory
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// Read a series of values from the same address in memory. This
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// call is identical to readi, save that the address is not incremented
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// from one read to the next. It is equivalent to:
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// for(int i=0; i<len; i++)
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// buf[i] = readio(a);
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// only it's faster in our implementation.
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//
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virtual void readz(const BUSW a, const int len, BUSW *buf) = 0;
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virtual void readz(const BUSW a, const int len, BUSW *buf) = 0;
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// Write a series of values into a block of memory on the FPGA
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// a is the address of the value to be written as it exists on the
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// wishbone bus within the FPGA.
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// len is the number of words to write
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// buf is a pointer to a place to from whence to grab the data
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// to be written.
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// This is equivalent to:
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// for(int i=0; i<len; i++)
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// writeio(a+i, buf[i]);
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// only it's faster in our implementation.
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virtual void writei(const BUSW a, const int len, const BUSW *buf) = 0;
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virtual void writei(const BUSW a, const int len, const BUSW *buf) = 0;
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// Write a series of values into the same address on the FPGA bus. This
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// call is identical to writei, save that the address is not incremented
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// from one write to the next. It is equivalent to:
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// for(int i=0; i<len; i++)
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// writeio(a, buf[i]);
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// only it's faster in our implementation.
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//
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virtual void writez(const BUSW a, const int len, const BUSW *buf) = 0;
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virtual void writez(const BUSW a, const int len, const BUSW *buf) = 0;
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// Query whether or not an interrupt has taken place
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// Query whether or not an interrupt has taken place
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virtual bool poll(void) = 0;
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virtual bool poll(void) = 0;
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virtual void reset_err(void) = 0;
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virtual void reset_err(void) = 0;
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// Clear any interrupt condition that has already been noticed by
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// Clear any interrupt condition that has already been noticed by
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// the interface, does not check for further interrupt
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// the interface, does not check for further interrupt
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virtual void clear(void) = 0;
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virtual void clear(void) = 0;
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virtual ~DEVBUS(void) { };
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};
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};
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#endif
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#endif
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