///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: regdefs.h
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// Filename: regdefs.h
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: This is a generic file that will need to be modified from one
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// Purpose: This is a generic file that will need to be modified from one
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// board implementation of the ZIP CPU to another. Specifically,
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// board implementation of the ZIP CPU to another. Specifically,
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// this file defines where items are on a WISHBONE bus. In this
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// this file defines where items are on a WISHBONE bus. In this
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// case, the Zip CPU debug addresses are found at 0x060 and 0x61.
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// case, the Zip CPU debug addresses are found at 0x060 and 0x61.
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// The Zip Debugger needs to know these addresses in order to
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// The Zip Debugger needs to know these addresses in order to
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// know what addresses to peek and poke to control and access the
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// know what addresses to peek and poke to control and access the
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// Zip CPU.
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// Zip CPU.
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//
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//
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//
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//
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// Creator: Dan Gisselquist
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// Creator: Dan Gisselquist
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// Gisselquist Tecnology, LLC
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// Gisselquist Technology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#ifndef REGDEFS_H
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#ifndef REGDEFS_H
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#define REGDEFS_H
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#define REGDEFS_H
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// Zip CPU Control and Debug registers
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// Zip CPU Control and Debug registers
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#define R_ZIPCTRL 0x00000060
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#define R_ZIPCTRL 0x00000060
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#define R_ZIPDATA 0x00000061
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#define R_ZIPDATA 0x00000061
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// RAM memory space
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// RAM memory space
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#define RAMBASE 0x00008000
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#define RAMBASE 0x00008000
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// Flash memory space
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// Flash memory space
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#define QSPIFLASH 0x00100000
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#define QSPIFLASH 0x00100000
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#define RAMLEN 0x08000
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#define RAMLEN 0x08000
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#define CPU_GO 0x0000
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#define CPU_GO 0x0000
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#define CPU_RESET 0x0040
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#define CPU_RESET 0x0040
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#define CPU_INT 0x0080
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#define CPU_INT 0x0080
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#define CPU_STEP 0x0100
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#define CPU_STEP 0x0100
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#define CPU_STALL 0x0200
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#define CPU_STALL 0x0200
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#define CPU_HALT 0x0400
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#define CPU_HALT 0x0400
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#define CPU_CLRCACHE 0x0800
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#define CPU_CLRCACHE 0x0800
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#define CPU_sR0 (0x0000|CPU_HALT)
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#define CPU_sR0 (0x0000|CPU_HALT)
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#define CPU_sSP (0x000d|CPU_HALT)
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#define CPU_sSP (0x000d|CPU_HALT)
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#define CPU_sCC (0x000e|CPU_HALT)
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#define CPU_sCC (0x000e|CPU_HALT)
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#define CPU_sPC (0x000f|CPU_HALT)
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#define CPU_sPC (0x000f|CPU_HALT)
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#define CPU_uR0 (0x0010|CPU_HALT)
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#define CPU_uR0 (0x0010|CPU_HALT)
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#define CPU_uSP (0x001d|CPU_HALT)
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#define CPU_uSP (0x001d|CPU_HALT)
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#define CPU_uCC (0x001e|CPU_HALT)
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#define CPU_uCC (0x001e|CPU_HALT)
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#define CPU_uPC (0x001f|CPU_HALT)
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#define CPU_uPC (0x001f|CPU_HALT)
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#endif
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#endif
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