///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Filename: zipdbg.cpp
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// Filename: zipdbg.cpp
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//
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//
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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//
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//
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// Purpose: Provide a simple debugger for the Zip CPU. This allows you
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// Purpose: Provide a simple debugger for the Zip CPU. This allows you
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// to halt the CPU, examine the registers, and even single step
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// to halt the CPU, examine the registers, and even single step
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// the CPU. It's not fully functional yet, as I would like to implement
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// the CPU. It's not fully functional yet, as I would like to implement
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// breakpoints and the ability to modify registers, but it's a good
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// breakpoints and the ability to modify registers, but it's a good
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// start.
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// start.
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//
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//
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// Commands while in the debugger are:
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// Commands while in the debugger are:
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// 'r' - RESET the CPU
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// 'r' - RESET the CPU
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// 'g' - Go. Release the CPU and exit the debugger.
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// 'g' - Go. Release the CPU and exit the debugger.
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// 'q' - Quit. Leave the debugger, while leaving the CPU halted.
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// 'q' - Quit. Leave the debugger, while leaving the CPU halted.
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// 's' - Single Step. Allows the CPU to advance by one instruction.
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// 's' - Single Step. Allows the CPU to advance by one instruction.
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//
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//
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//
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//
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//
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//
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// Creator: Dan Gisselquist, Ph.D.
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// Creator: Dan Gisselquist, Ph.D.
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// Gisselquist Tecnology, LLC
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// Gisselquist Tecnhology, LLC
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2015, Gisselquist Technology, LLC
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// Copyright (C) 2015, Gisselquist Technology, LLC
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//
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//
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// This program is free software (firmware): you can redistribute it and/or
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// This program is free software (firmware): you can redistribute it and/or
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// modify it under the terms of the GNU General Public License as published
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// modify it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or (at
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// by the Free Software Foundation, either version 3 of the License, or (at
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// your option) any later version.
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// your option) any later version.
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//
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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// for more details.
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//
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//
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// License: GPL, v3, as defined and found on www.gnu.org,
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// License: GPL, v3, as defined and found on www.gnu.org,
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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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#include <stdlib.h>
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#include <stdlib.h>
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#include <signal.h>
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#include <signal.h>
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#include <time.h>
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#include <time.h>
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#include <unistd.h>
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#include <unistd.h>
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|
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#include <ctype.h>
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#include <ctype.h>
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#include <ncurses.h>
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#include <ncurses.h>
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|
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// #include "twoc.h"
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// #include "twoc.h"
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// #include "qspiflashsim.h"
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// #include "qspiflashsim.h"
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#include "zopcodes.h"
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#include "zopcodes.h"
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#include "zparser.h"
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#include "zparser.h"
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#include "devbus.h"
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#include "devbus.h"
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#include "regdefs.h"
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#include "regdefs.h"
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// #include "port.h"
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// #include "port.h"
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|
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// No particular "parameters" need definition or redefinition here.
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// No particular "parameters" need definition or redefinition here.
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class ZIPPY : public DEVBUS {
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class ZIPPY : public DEVBUS {
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typedef DEVBUS::BUSW BUSW;
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typedef DEVBUS::BUSW BUSW;
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DEVBUS *m_fpga;
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DEVBUS *m_fpga;
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public:
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public:
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ZIPPY(DEVBUS *fpga) : m_fpga(fpga) {}
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ZIPPY(DEVBUS *fpga) : m_fpga(fpga) {}
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|
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void kill(void) { m_fpga->kill(); }
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void kill(void) { m_fpga->kill(); }
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void close(void) { m_fpga->close(); }
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void close(void) { m_fpga->close(); }
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void writeio(const BUSW a, const BUSW v) { m_fpga->writeio(a, v); }
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void writeio(const BUSW a, const BUSW v) { m_fpga->writeio(a, v); }
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BUSW readio(const BUSW a) { return m_fpga->readio(a); }
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BUSW readio(const BUSW a) { return m_fpga->readio(a); }
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void readi(const BUSW a, const int len, BUSW *buf) {
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void readi(const BUSW a, const int len, BUSW *buf) {
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return m_fpga->readi(a, len, buf); }
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return m_fpga->readi(a, len, buf); }
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void readz(const BUSW a, const int len, BUSW *buf) {
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void readz(const BUSW a, const int len, BUSW *buf) {
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return m_fpga->readz(a, len, buf); }
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return m_fpga->readz(a, len, buf); }
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void writei(const BUSW a, const int len, const BUSW *buf) {
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void writei(const BUSW a, const int len, const BUSW *buf) {
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return m_fpga->writei(a, len, buf); }
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return m_fpga->writei(a, len, buf); }
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void writez(const BUSW a, const int len, const BUSW *buf) {
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void writez(const BUSW a, const int len, const BUSW *buf) {
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return m_fpga->writez(a, len, buf); }
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return m_fpga->writez(a, len, buf); }
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bool poll(void) { return m_fpga->poll(); }
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bool poll(void) { return m_fpga->poll(); }
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void usleep(unsigned ms) { m_fpga->usleep(ms); }
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void usleep(unsigned ms) { m_fpga->usleep(ms); }
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void wait(void) { m_fpga->wait(); }
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void wait(void) { m_fpga->wait(); }
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bool bus_err(void) const { return m_fpga->bus_err(); }
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bool bus_err(void) const { return m_fpga->bus_err(); }
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void reset_err(void) { m_fpga->reset_err(); }
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void reset_err(void) { m_fpga->reset_err(); }
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void clear(void) { m_fpga->clear(); }
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void clear(void) { m_fpga->clear(); }
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|
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void reset(void) { writeio(R_ZIPCTRL, CPU_RESET|CPU_HALT); }
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void reset(void) { writeio(R_ZIPCTRL, CPU_RESET|CPU_HALT); }
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void step(void) { writeio(R_ZIPCTRL, CPU_STEP); }
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void step(void) { writeio(R_ZIPCTRL, CPU_STEP); }
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void go(void) { writeio(R_ZIPCTRL, CPU_GO); }
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void go(void) { writeio(R_ZIPCTRL, CPU_GO); }
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void halt(void) { writeio(R_ZIPCTRL, CPU_HALT); }
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void halt(void) { writeio(R_ZIPCTRL, CPU_HALT); }
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bool stalled(void) { return ((readio(R_ZIPCTRL)&CPU_STALL)==0); }
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bool stalled(void) { return ((readio(R_ZIPCTRL)&CPU_STALL)==0); }
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|
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void showval(int y, int x, const char *lbl, unsigned int v) {
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void showval(int y, int x, const char *lbl, unsigned int v) {
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mvprintw(y,x, "%s: 0x%08x", lbl, v);
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mvprintw(y,x, "%s: 0x%08x", lbl, v);
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}
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}
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|
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void dispreg(int y, int x, const char *n, unsigned int v) {
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void dispreg(int y, int x, const char *n, unsigned int v) {
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// 4,4,8,1 = 17 of 20, +3 = 19
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// 4,4,8,1 = 17 of 20, +3 = 19
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mvprintw(y, x, "%s: 0x%08x", n, v);
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mvprintw(y, x, "%s: 0x%08x", n, v);
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}
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}
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void showins(int y, const char *lbl,
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void showins(int y, const char *lbl,
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const int gie, const unsigned int pc) {
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const int gie, const unsigned int pc) {
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char line[80];
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char line[80];
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unsigned int v;
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unsigned int v;
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|
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mvprintw(y, 0, "%s: 0x%08x", lbl, pc);
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mvprintw(y, 0, "%s: 0x%08x", lbl, pc);
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|
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if (gie) attroff(A_BOLD);
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if (gie) attroff(A_BOLD);
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else attron(A_BOLD);
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else attron(A_BOLD);
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|
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line[0] = '\0';
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line[0] = '\0';
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try {
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try {
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v= readio(pc);
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v= readio(pc);
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zipi_to_string(v, line);
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zipi_to_string(v, line);
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printw(" 0x%08x", v);
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printw(" 0x%08x", v);
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printw(" %-24s", &line[1]);
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printw(" %-24s", &line[1]);
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} catch(BUSERR b) {
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} catch(BUSERR b) {
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printw(" 0x%08x %-24s", b.addr, "(Bus Error)");
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printw(" 0x%08x %-24s", b.addr, "(Bus Error)");
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}
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}
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attroff(A_BOLD);
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attroff(A_BOLD);
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}
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}
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unsigned int cmd_read(unsigned int a) {
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unsigned int cmd_read(unsigned int a) {
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writeio(R_ZIPCTRL, CPU_HALT|(a&0x3f));
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writeio(R_ZIPCTRL, CPU_HALT|(a&0x3f));
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while((readio(R_ZIPCTRL) & CPU_STALL) == 0)
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while((readio(R_ZIPCTRL) & CPU_STALL) == 0)
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;
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;
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return readio(R_ZIPDATA);
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return readio(R_ZIPDATA);
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}
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}
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|
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void read_state(void) {
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void read_state(void) {
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int ln= 0;
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int ln= 0;
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bool gie;
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bool gie;
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|
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mvprintw(ln,0, "Peripherals");
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mvprintw(ln,0, "Peripherals");
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mvprintw(ln,40, "CPU State: ");
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mvprintw(ln,40, "CPU State: ");
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{
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{
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unsigned int v = readio(R_ZIPDATA);
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unsigned int v = readio(R_ZIPDATA);
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if (v & 0x010000)
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if (v & 0x010000)
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printw("EXT-INT ");
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printw("EXT-INT ");
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if (v & 0x002000)
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if (v & 0x002000)
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printw("Supervisor Mod ");
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printw("Supervisor Mod ");
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if (v & 0x001000)
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if (v & 0x001000)
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printw("Sleeping ");
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printw("Sleeping ");
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if (v & 0x008000)
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if (v & 0x008000)
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printw("Break-Enabled ");
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printw("Break-Enabled ");
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}
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}
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ln++;
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ln++;
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showval(ln, 1, "PIC ", cmd_read(32+ 0));
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showval(ln, 1, "PIC ", cmd_read(32+ 0));
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showval(ln,21, "WDT ", cmd_read(32+ 1));
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showval(ln,21, "WDT ", cmd_read(32+ 1));
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showval(ln,41, "CACH", cmd_read(32+ 2));
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showval(ln,41, "CACH", cmd_read(32+ 2));
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showval(ln,61, "PIC2", cmd_read(32+ 3));
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showval(ln,61, "PIC2", cmd_read(32+ 3));
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ln++;
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ln++;
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showval(ln, 1, "TMRA", cmd_read(32+ 4));
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showval(ln, 1, "TMRA", cmd_read(32+ 4));
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showval(ln,21, "TMRB", cmd_read(32+ 5));
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showval(ln,21, "TMRB", cmd_read(32+ 5));
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showval(ln,41, "TMRC", cmd_read(32+ 6));
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showval(ln,41, "TMRC", cmd_read(32+ 6));
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showval(ln,61, "JIF ", cmd_read(32+ 7));
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showval(ln,61, "JIF ", cmd_read(32+ 7));
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|
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ln++;
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ln++;
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showval(ln, 1, "UTSK", cmd_read(32+12));
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showval(ln, 1, "UTSK", cmd_read(32+12));
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showval(ln,21, "UMST", cmd_read(32+13));
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showval(ln,21, "UMST", cmd_read(32+13));
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showval(ln,41, "UPST", cmd_read(32+14));
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showval(ln,41, "UPST", cmd_read(32+14));
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showval(ln,61, "UAST", cmd_read(32+15));
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showval(ln,61, "UAST", cmd_read(32+15));
|
|
|
ln++;
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ln++;
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ln++;
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ln++;
|
unsigned int cc = cmd_read(14);
|
unsigned int cc = cmd_read(14);
|
gie = (cc & 0x020);
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gie = (cc & 0x020);
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if (gie)
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if (gie)
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attroff(A_BOLD);
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attroff(A_BOLD);
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else
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else
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attron(A_BOLD);
|
attron(A_BOLD);
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mvprintw(ln, 0, "Supervisor Registers");
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mvprintw(ln, 0, "Supervisor Registers");
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ln++;
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ln++;
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|
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dispreg(ln, 1, "sR0 ", cmd_read(0));
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dispreg(ln, 1, "sR0 ", cmd_read(0));
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dispreg(ln,21, "sR1 ", cmd_read(1));
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dispreg(ln,21, "sR1 ", cmd_read(1));
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dispreg(ln,41, "sR2 ", cmd_read(2));
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dispreg(ln,41, "sR2 ", cmd_read(2));
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dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
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dispreg(ln,61, "sR3 ", cmd_read(3)); ln++;
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|
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dispreg(ln, 1, "sR4 ", cmd_read(4));
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dispreg(ln, 1, "sR4 ", cmd_read(4));
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dispreg(ln,21, "sR5 ", cmd_read(5));
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dispreg(ln,21, "sR5 ", cmd_read(5));
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dispreg(ln,41, "sR6 ", cmd_read(6));
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dispreg(ln,41, "sR6 ", cmd_read(6));
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dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
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dispreg(ln,61, "sR7 ", cmd_read(7)); ln++;
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|
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dispreg(ln, 1, "sR8 ", cmd_read( 8));
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dispreg(ln, 1, "sR8 ", cmd_read( 8));
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dispreg(ln,21, "sR9 ", cmd_read( 9));
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dispreg(ln,21, "sR9 ", cmd_read( 9));
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dispreg(ln,41, "sR10", cmd_read(10));
|
dispreg(ln,41, "sR10", cmd_read(10));
|
dispreg(ln,61, "sR11", cmd_read(11)); ln++;
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dispreg(ln,61, "sR11", cmd_read(11)); ln++;
|
|
|
dispreg(ln, 1, "sR12", cmd_read(12));
|
dispreg(ln, 1, "sR12", cmd_read(12));
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dispreg(ln,21, "sSP ", cmd_read(13));
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dispreg(ln,21, "sSP ", cmd_read(13));
|
|
|
mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
|
mvprintw(ln,41, "sCC :%s%s%s%s%s%s%s",
|
(cc & 0x040)?"STP":" ",
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(cc & 0x040)?"STP":" ",
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(cc & 0x020)?"GIE":" ",
|
(cc & 0x020)?"GIE":" ",
|
(cc & 0x010)?"SLP":" ",
|
(cc & 0x010)?"SLP":" ",
|
(cc&8)?"V":" ",
|
(cc&8)?"V":" ",
|
(cc&4)?"N":" ",
|
(cc&4)?"N":" ",
|
(cc&2)?"C":" ",
|
(cc&2)?"C":" ",
|
(cc&1)?"Z":" ");
|
(cc&1)?"Z":" ");
|
mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
|
mvprintw(ln,61, "sPC : 0x%08x", cmd_read(15));
|
ln++;
|
ln++;
|
|
|
if (gie)
|
if (gie)
|
attron(A_BOLD);
|
attron(A_BOLD);
|
else
|
else
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
mvprintw(ln, 0, "User Registers"); ln++;
|
mvprintw(ln, 0, "User Registers"); ln++;
|
dispreg(ln, 1, "uR0 ", cmd_read(16));
|
dispreg(ln, 1, "uR0 ", cmd_read(16));
|
dispreg(ln,21, "uR1 ", cmd_read(17));
|
dispreg(ln,21, "uR1 ", cmd_read(17));
|
dispreg(ln,41, "uR2 ", cmd_read(18));
|
dispreg(ln,41, "uR2 ", cmd_read(18));
|
dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
|
dispreg(ln,61, "uR3 ", cmd_read(19)); ln++;
|
|
|
dispreg(ln, 1, "uR4 ", cmd_read(20));
|
dispreg(ln, 1, "uR4 ", cmd_read(20));
|
dispreg(ln,21, "uR5 ", cmd_read(21));
|
dispreg(ln,21, "uR5 ", cmd_read(21));
|
dispreg(ln,41, "uR6 ", cmd_read(22));
|
dispreg(ln,41, "uR6 ", cmd_read(22));
|
dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
|
dispreg(ln,61, "uR7 ", cmd_read(23)); ln++;
|
|
|
dispreg(ln, 1, "uR8 ", cmd_read(24));
|
dispreg(ln, 1, "uR8 ", cmd_read(24));
|
dispreg(ln,21, "uR9 ", cmd_read(25));
|
dispreg(ln,21, "uR9 ", cmd_read(25));
|
dispreg(ln,41, "uR10", cmd_read(26));
|
dispreg(ln,41, "uR10", cmd_read(26));
|
dispreg(ln,61, "uR11", cmd_read(27)); ln++;
|
dispreg(ln,61, "uR11", cmd_read(27)); ln++;
|
|
|
dispreg(ln, 1, "uR12", cmd_read(28));
|
dispreg(ln, 1, "uR12", cmd_read(28));
|
dispreg(ln,21, "uSP ", cmd_read(29));
|
dispreg(ln,21, "uSP ", cmd_read(29));
|
cc = cmd_read(30);
|
cc = cmd_read(30);
|
mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
|
mvprintw(ln,41, "uCC :%s%s%s%s%s%s%s",
|
(cc&0x040)?"STP":" ",
|
(cc&0x040)?"STP":" ",
|
(cc&0x020)?"GIE":" ",
|
(cc&0x020)?"GIE":" ",
|
(cc&0x010)?"SLP":" ",
|
(cc&0x010)?"SLP":" ",
|
(cc&8)?"V":" ",
|
(cc&8)?"V":" ",
|
(cc&4)?"N":" ",
|
(cc&4)?"N":" ",
|
(cc&2)?"C":" ",
|
(cc&2)?"C":" ",
|
(cc&1)?"Z":" ");
|
(cc&1)?"Z":" ");
|
mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
|
mvprintw(ln,61, "uPC : 0x%08x", cmd_read(31));
|
|
|
attroff(A_BOLD);
|
attroff(A_BOLD);
|
ln+=2;
|
ln+=2;
|
|
|
ln+=3;
|
ln+=3;
|
BUSW pc = cmd_read((gie)?31:15);
|
BUSW pc = cmd_read((gie)?31:15);
|
showins(ln, "I ", gie, pc+2); ln++;
|
showins(ln, "I ", gie, pc+2); ln++;
|
showins(ln, "Dc", gie, pc+1); ln++;
|
showins(ln, "Dc", gie, pc+1); ln++;
|
showins(ln, "Op", gie, pc ); ln++;
|
showins(ln, "Op", gie, pc ); ln++;
|
showins(ln, "Al", gie, pc-1); ln++;
|
showins(ln, "Al", gie, pc-1); ln++;
|
}
|
}
|
};
|
};
|
|
|
DEVBUS *m_fpga;
|
DEVBUS *m_fpga;
|
|
|
int main(int argc, char **argv) {
|
int main(int argc, char **argv) {
|
// FPGAOPEN(m_fpga);
|
// FPGAOPEN(m_fpga);
|
ZIPPY *zip = new ZIPPY(m_fpga);
|
ZIPPY *zip = new ZIPPY(m_fpga);
|
|
|
initscr();
|
initscr();
|
raw();
|
raw();
|
noecho();
|
noecho();
|
keypad(stdscr, true);
|
keypad(stdscr, true);
|
|
|
int chv;
|
int chv;
|
bool done = false;
|
bool done = false;
|
|
|
zip->halt();
|
zip->halt();
|
for(int i=0; (i<5)&&(zip->stalled()); i++)
|
for(int i=0; (i<5)&&(zip->stalled()); i++)
|
;
|
;
|
if (!zip->stalled())
|
if (!zip->stalled())
|
zip->read_state();
|
zip->read_state();
|
while(!done) {
|
while(!done) {
|
chv = getch();
|
chv = getch();
|
switch(chv) {
|
switch(chv) {
|
case 'g': case 'G':
|
case 'g': case 'G':
|
m_fpga->writeio(R_ZIPCTRL, CPU_GO);
|
m_fpga->writeio(R_ZIPCTRL, CPU_GO);
|
// We just released the CPU, so we're now done.
|
// We just released the CPU, so we're now done.
|
done = true;
|
done = true;
|
break;
|
break;
|
case 'q': case 'Q':
|
case 'q': case 'Q':
|
done = true;
|
done = true;
|
break;
|
break;
|
case 'r': case 'R':
|
case 'r': case 'R':
|
zip->reset();
|
zip->reset();
|
erase();
|
erase();
|
break;
|
break;
|
case 's': case 'S':
|
case 's': case 'S':
|
zip->step();
|
zip->step();
|
break;
|
break;
|
case ERR:
|
case ERR:
|
default:
|
default:
|
;
|
;
|
}
|
}
|
|
|
if (zip->stalled())
|
if (zip->stalled())
|
erase();
|
erase();
|
else
|
else
|
zip->read_state();
|
zip->read_state();
|
}
|
}
|
|
|
endwin();
|
endwin();
|
}
|
}
|
|
|
|
|
