B_Reg Entity Reference

Inheritance diagram for B_Reg:
behave struct MP

List of all members.



Architectures

behave Architecture

Libraries

ieee 

Packages

std_logic_1164 

Ports

d  in std_logic_vector ( 7 downto 0 )
 8-bit B input from W-bus
q  out std_logic_vector ( 7 downto 0 )
 8-bit B output to Adder-Subtractor
clk  in std_logic
 Rising edge clock.
clr  in std_logic
 Active high asynchronous clear.
lb  in std_logic
 Active low load B content into output.

The documentation for this class was generated from the following file:
Generated on Wed Apr 11 09:49:20 2012 for Microprocessor 8-bit by  doxygen 1.6.3