MP Entity Reference

Inheritance diagram for MP:
struct O ROM_16_8 PC MAR IRDec IR CU B_Reg ALU AC

List of all members.



Architectures

struct Architecture

Libraries

ieee 

Packages

std_logic_1164 
std_logic_arith 

Ports

clk  in std_logic
 Active high asynchronous clear.
clr  in std_logic
 Rising edge clock.
hlt  out std_logic
 Halt signal to stop processing data.
q3  out std_logic_vector ( 7 downto 0 )
 8-bit output

Member Data Documentation

ieee library [Library]
Architecture.png

Reimplemented from AC.


The documentation for this class was generated from the following file:
Generated on Wed Apr 11 09:49:21 2012 for Microprocessor 8-bit by  doxygen 1.6.3