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Test_MP Entity Reference
Inheritance diagram for Test_MP:
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legend
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Collaboration diagram for Test_MP:
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legend
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List of all members.
Architectures
Behavioral
Architecture
Libraries
IEEE
Packages
STD_LOGIC_1164
Ports
CLEAR
in
std_logic
CLOCK
in
std_logic
HALT
out
std_logic
SCLOCK
out
std_ulogic
MP_Binary_Out
out
std_logic_vector
(
7
downto
0
)
The documentation for this class was generated from the following file:
testFPGA/Test_MP.vhd
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Generated on Tue Apr 10 20:26:44 2012 for Microprocessor 8-bit by
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