Project Settings |
---|
Project Name | proj_1 | Implementation Name | impl1 |
Top Module | display_driver_wrapper | Pipelining | 1 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 1000 | Disable I/O Insertion | 0 |
Disable Sequential Optimizations | 0 | Clock Conversion | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
13 |
1 |
0 |
- |
0m:00s |
- |
18-Jan-17 01:08:13 |
(premap) | Complete |
2 |
1 |
0 |
0m:00s |
0m:00s |
141MB |
18-Jan-17 01:08:15 |
(fpga_mapper) | Complete |
11 |
1 |
0 |
0m:01s |
0m:01s |
145MB |
18-Jan-17 01:08:17 |
Multi-srs Generator |
Complete | | | | | | | 18-Jan-17 01:08:14 |
Area Summary |
|
Register bits | 13 |
I/O cells | 18 |
Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
ORCA LUTs
(total_luts) | 4 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
display_driver_wrapper|clk | 433.9 MHz | 368.8 MHz | -0.407 |
Optimizations Summary |
Combined Clock Conversion | 1 / 0 |
| |
|