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Description of single_port memory and test environment.

Abstract:

A single port memory with testbench is described. The memory is implemented as three different architectures.

Port Interface:

Functional Description:

The single_port memory is implemented as three different architecures. The first architecture is called ArrayMemNoFlag, and implements the memory core as an array of STD_LOGIC_VECTOR. The memory is asynchronous and triggered on rnw'transaction. When rnw = '0', the data on bus "d" is loaded into the memory at the location specified by the addres bus "a". When rnw = '1', the data located in memory address "a" is loaded onto the output data bus "q". If a memory location is read which was not written to during the current simulation, 'U' are loaded onto the memory bus.

The second architecture is called ArrayMem, and implements the memory core as an array of BIT_VECTOR. This arrangement allows less workstation memory to be used than the ArrayMemNoFlag architecture. The memory is asynchronous and triggered on rnw'transaction. When rnw = '0', the data on bus "d" is loaded into the memory at the location specified by the addres bus "a". When rnw = '1', the data located in memory address "a" is loaded onto the output data bus "q". If a memory location is read which was not written to during the current simulation, 'U' are loaded onto the memory bus.

The third architecture is called LinkedList, and implements the memory core as a linked list of arrays of BIT_VECTOR. Each array in the linked list is a page of memory whose size is specified in single_port_pkg. This arrangement allows less workstation memory to be used than either the ArrayMemNoFlag or ArrayMem architectures. The memory is asynchronous and triggered on rnw'transaction. When rnw = '0', the data on bus "d" is loaded into the memory at the location specified by the addres bus "a". When rnw = '1', the data located in memory address "a" is loaded onto the output data bus "q". If a memory location is read which was not written to during the current simulation, 'U' are loaded onto the memory bus. To de-allocate the memory in the linked list, set dealloc_mem to true.

Functional Timing:

The single port memory is asynchronous and is triggered on rnw'transaction. When rnw is cleared to '0', the write occurs at the same time as rnw'transaction. When a read occurs, with rnw = '1' , data appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample timing diagram illustrates both a read and write operation.

Testbench Description:

The test bench is arranged as a client server architecture as specified by Bergeron¹. A diagram illustrating the testbench is given below.


Two tests are specified in tc_single_port component. The first test writes data to two logical memory pages, and then reads them back verifying the correct data. The test case writes an error message to the console for every miscompare. The second case verifies that the single_port memory model outputs unknowns to the q bus if a read occurs for an unwritten memory location. Six configurations are specified in the test bench architecture tb_single_port, running both tests for each single_port architecture.

Usage:

A Makefile is used to compile and run all of the tests in a Unix or like environment, such as Cygwin. The compilation and simulation is targetted to the SymphonyEDA tool available at www.symphonyeda.com .

The source files and Makefile are located in {top}/VHDL

To compile: make com

To simulate all of the tests: make sim

To clean the compiled library: make clean

To run tests individually:

• make ll_error
• make ll_main
• make mem_main
  
• make mem_error
  
• make memnoflag_main
  
• make memnoflag_error
  

Please contact Robert Paley at rpaley_yid@opencores.org if you have any questions or comments.