#
# Copyright 2012, Sinclair R.F., Inc.
#
# Test bench for latch peripheral.
#

ARCHITECTURE    core/9x8 Verilog
INSTRUCTION     64
DATA_STACK      32
RETURN_STACK    16

PERIPHERAL      latch           outport_latch=O_9LATCH \
                                outport_addr=O_9ADDR \
                                inport=I_9READ \
                                insignal=i_9value \
                                width=9

PERIPHERAL      latch           outport_latch=O_24LATCH \
                                outport_addr=O_24ADDR \
                                inport=I_24READ \
                                insignal=i_24value \
                                width=24

OUTPORT 8-bit,strobe o_test,o_test_wr O_TEST

OUTPORT 1-bit o_done O_DONE

ASSEMBLY tb_latch.s