#
# Copyright 2013, Sinclair R.F., Inc.
#
# Test bench for timer peripheral.
#

ARCHITECTURE    core/9x8 Verilog
INSTRUCTION     64
DATA_STACK      16
RETURN_STACK    16

PARAMETER       G_CLK_FREQ_HZ   14_745_600
PARAMETER       G_BAUD          230400

PERIPHERAL      timer           inport=I_TIMER_0 ratemethod=G_CLK_FREQ_HZ/G_BAUD

PERIPHERAL      timer           inport=I_TIMER_1 ratemethod=G_CLK_FREQ_HZ/28800

PERIPHERAL      timer           inport=I_TIMER_2 ratemethod=G_CLK_FREQ_HZ/1000

PERIPHERAL      timer           inport=I_TIMER_3 ratemethod=10_000

OUTPORT 2-bit,strobe o_event,o_event_wr O_EVENT
OUTPORT 1-bit o_done  O_DONE

ASSEMBLY tb_timer.s