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[/] [System09/] [trunk/] [rtl/] [System09_Digilent_Atlys/] [system09.xise] - Rev 180
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xil_pn:valueState="default"/><property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Other Ngdbuild Command Line Options" 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xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Output File Name" xil_pn:value="system09" xil_pn:valueState="default"/><property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true" xil_pn:valueState="non-default"/><property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/><property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/><property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Perform Timing-Driven Packing and Placement" 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xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/><property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/><property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/><property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/><property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/><property 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These should not be modified.--><!-- --><property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_DesignName" xil_pn:value="System09" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/><property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/><property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-05-18T18:01:32" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3E1B092C13974DD5BACAD4E9115A1158" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_xawInstTempTargetLang" xil_pn:value="VHDL" xil_pn:valueState="non-default"/></properties><bindings/><libraries/><autoManagedFiles><!-- The following files are identified by `include statements in verilog --><!-- source files and are automatically managed by Project Navigator. --><!-- --><!-- Do not hand-edit this section, as it will be overwritten when the --><!-- project is analyzed based on files automatically identified as --><!-- include files. --></autoManagedFiles></project>
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