Subversion Repositories dirac

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: output_unit.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "output_unit.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "output_unit"
Output Format                      : NGC
Target Device                      : xc2v2000-6-bg575

---- Source Options
Top Module Name                    : output_unit
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : output_unit.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/OUTPUT_UNIT.vhd" in Library work.
Architecture rtl of Entity output_unit is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <output_unit> (Architecture <rtl>).
Entity <output_unit> analyzed. Unit <output_unit> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <output_unit>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/OUTPUT_UNIT.vhd".
    Found 1-bit register for signal <DELAYED>.
    Found 1-bit xor2 for signal <OUTVALUE>.
    Summary:
        inferred   1 D-type flip-flop(s).
Unit <output_unit> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
 1-bit register                    : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <output_unit> ...
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block output_unit, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : output_unit.ngr
Top Level Output File Name         : output_unit
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 9

Macro Statistics :
# Registers                        : 1
#      1-bit register              : 1

Cell Usage :
# BELS                             : 4
#      LUT2                        : 2
#      LUT4                        : 1
#      LUT4_D                      : 1
# FlipFlops/Latches                : 1
#      FD                          : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 8
#      IBUF                        : 4
#      OBUF                        : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v2000bg575-6 

 Number of Slices:                       2  out of  10752     0%  
 Number of Slice Flip Flops:             1  out of  21504     0%  
 Number of 4 input LUTs:                 4  out of  21504     0%  
 Number of bonded IOBs:                  9  out of    408     2%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLOCK                              | BUFGP                  | 1     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 1.673ns (Maximum Frequency: 597.550MHz)
   Minimum input arrival time before clock: 2.053ns
   Maximum output required time after clock: 5.699ns
   Maximum combinational path delay: 6.630ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
  Clock period: 1.673ns (frequency: 597.550MHz)
  Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Delay:               1.673ns (Levels of Logic = 1)
  Source:            DELAYED (FF)
  Destination:       DELAYED (FF)
  Source Clock:      CLOCK rising
  Destination Clock: CLOCK rising

  Data Path: DELAYED to DELAYED
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.449   0.584  DELAYED (DELAYED)
     LUT4_D:I3->LO         1   0.347   0.000  SENDING1 (N3)
     FD:D                      0.293          DELAYED
    ----------------------------------------
    Total                      1.673ns (1.089ns logic, 0.584ns route)
                                       (65.1% logic, 34.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
  Total number of paths / destination ports: 3 / 1
-------------------------------------------------------------------------
Offset:              2.053ns (Levels of Logic = 2)
  Source:            FOLLOW (PAD)
  Destination:       DELAYED (FF)
  Destination Clock: CLOCK rising

  Data Path: FOLLOW to DELAYED
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   0.653   0.761  FOLLOW_IBUF (FOLLOW_IBUF)
     LUT4_D:I0->LO         1   0.347   0.000  SENDING1 (N3)
     FD:D                      0.293          DELAYED
    ----------------------------------------
    Total                      2.053ns (1.293ns logic, 0.761ns route)
                                       (63.0% logic, 37.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset:              5.699ns (Levels of Logic = 2)
  Source:            DELAYED (FF)
  Destination:       SHIFT (PAD)
  Source Clock:      CLOCK rising

  Data Path: DELAYED to SHIFT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.449   0.778  DELAYED (DELAYED)
     LUT2:I0->O            1   0.347   0.383  SHIFT1 (SHIFT_OBUF)
     OBUF:I->O                 3.743          SHIFT_OBUF (SHIFT)
    ----------------------------------------
    Total                      5.699ns (4.539ns logic, 1.160ns route)
                                       (79.6% logic, 20.4% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 8 / 3
-------------------------------------------------------------------------
Delay:               6.630ns (Levels of Logic = 4)
  Source:            RESET (PAD)
  Destination:       DATA_OUT (PAD)

  Data Path: RESET to DATA_OUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.653   0.743  RESET_IBUF (RESET_IBUF)
     LUT2:I0->O            1   0.347   0.414  DATA_OUT1 (N0)
     LUT4:I3->O            1   0.347   0.383  DATA_OUT2 (DATA_OUT_OBUF)
     OBUF:I->O                 3.743          DATA_OUT_OBUF (DATA_OUT)
    ----------------------------------------
    Total                      6.630ns (5.090ns logic, 1.540ns route)
                                       (76.8% logic, 23.2% route)

=========================================================================
CPU : 4.45 / 4.81 s | Elapsed : 4.00 / 5.00 s
 
--> 

Total memory usage is 120124 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)