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[/] [eco32/] [trunk/] [fpga/] [mc/] [boards/] [s3e-500/] [doc/] [dac/] [README] - Rev 301

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Timing Parameters
-----------------

clk = 50 MHz (20 nsec)
sck = clk / 2 = 25 MHz (40 nsec)
50 bits per sample (a pair of 16 bit values)
repeated after 512 sck cycles

==>

fs = 48.828 kHz
less than 10% of SPI capacity used

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