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[/] [ethmac/] [tags/] [rel_2/] [rtl/] [verilog/] [eth_registers.v] - Rev 342
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////////////////////////////////////////////////////////////////////// //// //// //// eth_registers.v //// //// //// //// This file is part of the Ethernet IP core project //// //// http://www.opencores.org/projects/ethmac/ //// //// //// //// Author(s): //// //// - Igor Mohor (igorM@opencores.org) //// //// //// //// All additional information is avaliable in the Readme.txt //// //// file. //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.13 2002/02/26 16:18:09 mohor // Reset values are passed to registers through parameters // // Revision 1.12 2002/02/17 13:23:42 mohor // Define missmatch fixed. // // Revision 1.11 2002/02/16 14:03:44 mohor // Registered trimmed. Unused registers removed. // // Revision 1.10 2002/02/15 11:08:25 mohor // File format fixed a bit. // // Revision 1.9 2002/02/14 20:19:41 billditt // Modified for Address Checking, // addition of eth_addrcheck.v // // Revision 1.8 2002/02/12 17:01:19 mohor // HASH0 and HASH1 registers added. // Revision 1.7 2002/01/23 10:28:16 mohor // Link in the header changed. // // Revision 1.6 2001/12/05 15:00:16 mohor // RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors // instead of the number of RX descriptors). // // Revision 1.5 2001/12/05 10:22:19 mohor // ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. // // Revision 1.4 2001/10/19 08:43:51 mohor // eth_timescale.v changed to timescale.v This is done because of the // simulation of the few cores in a one joined project. // // Revision 1.3 2001/10/18 12:07:11 mohor // Status signals changed, Adress decoding changed, interrupt controller // added. // // Revision 1.2 2001/09/24 15:02:56 mohor // Defines changed (All precede with ETH_). Small changes because some // tools generate warnings when two operands are together. Synchronization // between two clocks domains in eth_wishbonedma.v is changed (due to ASIC // demands). // // Revision 1.1 2001/08/06 14:44:29 mohor // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). // Include files fixed to contain no path. // File names and module names changed ta have a eth_ prologue in the name. // File eth_timescale.v is used to define timescale // All pin names on the top module are changed to contain _I, _O or _OE at the end. // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O // and Mdo_OE. The bidirectional signal must be created on the top level. This // is done due to the ASIC tools. // // Revision 1.2 2001/08/02 09:25:31 mohor // Unconnected signals are now connected. // // Revision 1.1 2001/07/30 21:23:42 mohor // Directory structure changed. Files checked and joind together. // // // // // // `include "eth_defines.v" `include "timescale.v" module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn, r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG, r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn, TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ, r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet, r_CollValid, r_TxFlow, r_RxFlow, r_PassAll, r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, LinkFail, r_MAC, WCtrlDataStart, RStatStart, UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o, r_HASH0, r_HASH1 ); parameter Tp = 1; input [31:0] DataIn; input [7:0] Address; input Rw; input Cs; input Clk; input Reset; input WCtrlDataStart; input RStatStart; input UpdateMIIRX_DATAReg; input [15:0] Prsd; output [31:0] DataOut; reg [31:0] DataOut; output r_RecSmall; output r_Pad; output r_HugEn; output r_CrcEn; output r_DlyCrcEn; output r_Rst; output r_FullD; output r_ExDfrEn; output r_NoBckof; output r_LoopBck; output r_IFG; output r_Pro; output r_Iam; output r_Bro; output r_NoPre; output r_TxEn; output r_RxEn; output [31:0] r_HASH0; output [31:0] r_HASH1; input TxB_IRQ; input TxE_IRQ; input RxB_IRQ; input RxE_IRQ; input Busy_IRQ; input TxC_IRQ; input RxC_IRQ; output [6:0] r_IPGT; output [6:0] r_IPGR1; output [6:0] r_IPGR2; output [15:0] r_MinFL; output [15:0] r_MaxFL; output [3:0] r_MaxRet; output [5:0] r_CollValid; output r_TxFlow; output r_RxFlow; output r_PassAll; output r_MiiMRst; output r_MiiNoPre; output [7:0] r_ClkDiv; output r_WCtrlData; output r_RStat; output r_ScanStat; output [4:0] r_RGAD; output [4:0] r_FIAD; output [15:0]r_CtrlData; input NValid_stat; input Busy_stat; input LinkFail; output [47:0]r_MAC; output [7:0] r_TxBDNum; output TX_BD_NUM_Wr; output int_o; reg irq_txb; reg irq_txe; reg irq_rxb; reg irq_rxe; reg irq_busy; reg irq_txc; reg irq_rxc; wire Write = Cs & Rw; wire Read = Cs & ~Rw; wire MODER_Wr = (Address == `ETH_MODER_ADR ) & Write; wire INT_SOURCE_Wr = (Address == `ETH_INT_SOURCE_ADR ) & Write; wire INT_MASK_Wr = (Address == `ETH_INT_MASK_ADR ) & Write; wire IPGT_Wr = (Address == `ETH_IPGT_ADR ) & Write; wire IPGR1_Wr = (Address == `ETH_IPGR1_ADR ) & Write; wire IPGR2_Wr = (Address == `ETH_IPGR2_ADR ) & Write; wire PACKETLEN_Wr = (Address == `ETH_PACKETLEN_ADR ) & Write; wire COLLCONF_Wr = (Address == `ETH_COLLCONF_ADR ) & Write; wire CTRLMODER_Wr = (Address == `ETH_CTRLMODER_ADR ) & Write; wire MIIMODER_Wr = (Address == `ETH_MIIMODER_ADR ) & Write; wire MIICOMMAND_Wr = (Address == `ETH_MIICOMMAND_ADR ) & Write; wire MIIADDRESS_Wr = (Address == `ETH_MIIADDRESS_ADR ) & Write; wire MIITX_DATA_Wr = (Address == `ETH_MIITX_DATA_ADR ) & Write; wire MIIRX_DATA_Wr = UpdateMIIRX_DATAReg; wire MIISTATUS_Wr = (Address == `ETH_MIISTATUS_ADR ) & Write; wire MAC_ADDR0_Wr = (Address == `ETH_MAC_ADDR0_ADR ) & Write; wire MAC_ADDR1_Wr = (Address == `ETH_MAC_ADDR1_ADR ) & Write; wire HASH0_Wr = (Address == `ETH_HASH0_ADR ) & Write; wire HASH1_Wr = (Address == `ETH_HASH1_ADR ) & Write; assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR ) & Write; wire [31:0] MODEROut; wire [31:0] INT_SOURCEOut; wire [31:0] INT_MASKOut; wire [31:0] IPGTOut; wire [31:0] IPGR1Out; wire [31:0] IPGR2Out; wire [31:0] PACKETLENOut; wire [31:0] COLLCONFOut; wire [31:0] CTRLMODEROut; wire [31:0] MIIMODEROut; wire [31:0] MIICOMMANDOut; wire [31:0] MIIADDRESSOut; wire [31:0] MIITX_DATAOut; wire [31:0] MIIRX_DATAOut; wire [31:0] MIISTATUSOut; wire [31:0] MAC_ADDR0Out; wire [31:0] MAC_ADDR1Out; wire [31:0] TX_BD_NUMOut; wire [31:0] HASH0Out; wire [31:0] HASH1Out; eth_register #(17, `ETH_MODER_DEF) MODER (.DataIn(DataIn[16:0]), .DataOut(MODEROut[16:0]), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset)); assign MODEROut[31:17] = 0; eth_register #(7, `ETH_INT_MASK_DEF) INT_MASK (.DataIn(DataIn[6:0]), .DataOut(INT_MASKOut[6:0]), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset)); assign INT_MASKOut[31:7] = 0; eth_register #(7, `ETH_IPGT_DEF) IPGT (.DataIn(DataIn[6:0]), .DataOut(IPGTOut[6:0]), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset)); assign IPGTOut[31:7] = 0; eth_register #(7, `ETH_IPGR1_DEF) IPGR1 (.DataIn(DataIn[6:0]), .DataOut(IPGR1Out[6:0]), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset)); assign IPGR1Out[31:7] = 0; eth_register #(7, `ETH_IPGR2_DEF) IPGR2 (.DataIn(DataIn[6:0]), .DataOut(IPGR2Out[6:0]), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset)); assign IPGR2Out[31:7] = 0; eth_register #(32, `ETH_PACKETLEN_DEF) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset)); eth_register #(6, `ETH_COLLCONF0_DEF) COLLCONF0 (.DataIn(DataIn[5:0]), .DataOut(COLLCONFOut[5:0]), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset)); eth_register #(4, `ETH_COLLCONF1_DEF) COLLCONF1 (.DataIn(DataIn[19:16]),.DataOut(COLLCONFOut[19:16]), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset)); assign COLLCONFOut[15:6] = 0; assign COLLCONFOut[31:20] = 0; eth_register #(8, `ETH_TX_BD_NUM_DEF) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset)); assign TX_BD_NUMOut[31:8] = 24'h0; eth_register #(3, `ETH_CTRLMODER_DEF) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset)); assign CTRLMODEROut[31:3] = 29'h0; eth_register #(11, `ETH_MIIMODER_DEF) MIIMODER (.DataIn(DataIn[10:0]), .DataOut(MIIMODEROut[10:0]), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset)); assign MIIMODEROut[31:11] = 0; eth_register #(1, 0) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart)); eth_register #(1, 0) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart)); eth_register #(1, 0) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset)); assign MIICOMMANDOut[31:3] = 29'h0; eth_register #(5, `ETH_MIIADDRESS0_DEF) MIIADDRESS0 (.DataIn(DataIn[4:0]), .DataOut(MIIADDRESSOut[4:0]), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset)); eth_register #(5, `ETH_MIIADDRESS1_DEF) MIIADDRESS1 (.DataIn(DataIn[12:8]), .DataOut(MIIADDRESSOut[12:8]),.Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset)); assign MIIADDRESSOut[7:5] = 0; assign MIIADDRESSOut[31:13] = 0; eth_register #(16, `ETH_MIITX_DATA_DEF) MIITX_DATA (.DataIn(DataIn[15:0]), .DataOut(MIITX_DATAOut[15:0]),.Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset)); assign MIITX_DATAOut[31:16] = 0; eth_register #(16, `ETH_MIIRX_DATA_DEF) MIIRX_DATA (.DataIn(Prsd[15:0]), .DataOut(MIIRX_DATAOut[15:0]),.Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset)); assign MIIRX_DATAOut[31:16] = 0; eth_register #(32, `ETH_MAC_ADDR0_DEF) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset)); eth_register #(16, `ETH_MAC_ADDR1_DEF) MAC_ADDR1 (.DataIn(DataIn[15:0]), .DataOut(MAC_ADDR1Out[15:0]), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset)); assign MAC_ADDR1Out[31:16] = 0; eth_register #(32, `ETH_HASH0_DEF) RXHASH0 (.DataIn(DataIn), .DataOut(HASH0Out), .Write(HASH0_Wr), .Clk(Clk), .Reset(Reset)); eth_register #(32, `ETH_HASH1_DEF) RXHASH1 (.DataIn(DataIn), .DataOut(HASH1Out), .Write(HASH1_Wr), .Clk(Clk), .Reset(Reset)); reg LinkFailRegister; wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read; reg ResetLinkFailRegister_q1; reg ResetLinkFailRegister_q2; always @ (posedge Clk or posedge Reset) begin if(Reset) begin LinkFailRegister <= #Tp 0; ResetLinkFailRegister_q1 <= #Tp 0; ResetLinkFailRegister_q2 <= #Tp 0; end else begin ResetLinkFailRegister_q1 <= #Tp ResetLinkFailRegister; ResetLinkFailRegister_q2 <= #Tp ResetLinkFailRegister_q1; if(LinkFail) LinkFailRegister <= #Tp 1; if(~ResetLinkFailRegister_q1 & ResetLinkFailRegister_q2) LinkFailRegister <= #Tp 0; end end always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or HASH0Out or HASH1Out) begin if(Read) // read begin case(Address) `ETH_MODER_ADR : DataOut<=MODEROut; `ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut; `ETH_INT_MASK_ADR : DataOut<=INT_MASKOut; `ETH_IPGT_ADR : DataOut<=IPGTOut; `ETH_IPGR1_ADR : DataOut<=IPGR1Out; `ETH_IPGR2_ADR : DataOut<=IPGR2Out; `ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut; `ETH_COLLCONF_ADR : DataOut<=COLLCONFOut; `ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut; `ETH_MIIMODER_ADR : DataOut<=MIIMODEROut; `ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut; `ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut; `ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut; `ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut; `ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut; `ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out; `ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out; `ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut; `ETH_HASH0_ADR : DataOut<=HASH0Out; `ETH_HASH1_ADR : DataOut<=HASH1Out; default: DataOut<=32'h0; endcase end else DataOut<=32'h0; end assign r_RecSmall = MODEROut[16]; assign r_Pad = MODEROut[15]; assign r_HugEn = MODEROut[14]; assign r_CrcEn = MODEROut[13]; assign r_DlyCrcEn = MODEROut[12]; assign r_Rst = MODEROut[11]; assign r_FullD = MODEROut[10]; assign r_ExDfrEn = MODEROut[9]; assign r_NoBckof = MODEROut[8]; assign r_LoopBck = MODEROut[7]; assign r_IFG = MODEROut[6]; assign r_Pro = MODEROut[5]; assign r_Iam = MODEROut[4]; assign r_Bro = MODEROut[3]; assign r_NoPre = MODEROut[2]; assign r_TxEn = MODEROut[1]; assign r_RxEn = MODEROut[0]; assign r_IPGT[6:0] = IPGTOut[6:0]; assign r_IPGR1[6:0] = IPGR1Out[6:0]; assign r_IPGR2[6:0] = IPGR2Out[6:0]; assign r_MinFL[15:0] = PACKETLENOut[31:16]; assign r_MaxFL[15:0] = PACKETLENOut[15:0]; assign r_MaxRet[3:0] = COLLCONFOut[19:16]; assign r_CollValid[5:0] = COLLCONFOut[5:0]; assign r_TxFlow = CTRLMODEROut[2]; assign r_RxFlow = CTRLMODEROut[1]; assign r_PassAll = CTRLMODEROut[0]; assign r_MiiMRst = MIIMODEROut[10]; assign r_MiiNoPre = MIIMODEROut[8]; assign r_ClkDiv[7:0] = MIIMODEROut[7:0]; assign r_WCtrlData = MIICOMMANDOut[2]; assign r_RStat = MIICOMMANDOut[1]; assign r_ScanStat = MIICOMMANDOut[0]; assign r_RGAD[4:0] = MIIADDRESSOut[12:8]; assign r_FIAD[4:0] = MIIADDRESSOut[4:0]; assign r_CtrlData[15:0] = MIITX_DATAOut[15:0]; assign MIISTATUSOut[31:10] = 22'h0 ; assign MIISTATUSOut[9] = NValid_stat ; assign MIISTATUSOut[8] = Busy_stat ; assign MIISTATUSOut[7:1]= 7'h0 ; assign MIISTATUSOut[0] = LinkFailRegister ; assign r_MAC[31:0] = MAC_ADDR0Out[31:0]; assign r_MAC[47:32] = MAC_ADDR1Out[15:0]; assign r_HASH1[31:0] = HASH1Out; assign r_HASH0[31:0] = HASH0Out; assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0]; // Interrupt generation always @ (posedge Clk or posedge Reset) begin if(Reset) irq_txb <= 1'b0; else if(TxB_IRQ) irq_txb <= #Tp 1'b1; else if(INT_SOURCE_Wr & DataIn[0]) irq_txb <= #Tp 1'b0; end always @ (posedge Clk or posedge Reset) begin if(Reset) irq_txe <= 1'b0; else if(TxE_IRQ) irq_txe <= #Tp 1'b1; else if(INT_SOURCE_Wr & DataIn[1]) irq_txe <= #Tp 1'b0; end always @ (posedge Clk or posedge Reset) begin if(Reset) irq_rxb <= 1'b0; else if(RxB_IRQ) irq_rxb <= #Tp 1'b1; else if(INT_SOURCE_Wr & DataIn[2]) irq_rxb <= #Tp 1'b0; end always @ (posedge Clk or posedge Reset) begin if(Reset) irq_rxe <= 1'b0; else if(RxE_IRQ) irq_rxe <= #Tp 1'b1; else if(INT_SOURCE_Wr & DataIn[3]) irq_rxe <= #Tp 1'b0; end always @ (posedge Clk or posedge Reset) begin if(Reset) irq_busy <= 1'b0; else if(Busy_IRQ) irq_busy <= #Tp 1'b1; else if(INT_SOURCE_Wr & DataIn[4]) irq_busy <= #Tp 1'b0; end always @ (posedge Clk or posedge Reset) begin if(Reset) irq_txc <= 1'b0; else if(TxC_IRQ) irq_txc <= #Tp 1'b1; else if(INT_SOURCE_Wr & DataIn[5]) irq_txc <= #Tp 1'b0; end always @ (posedge Clk or posedge Reset) begin if(Reset) irq_rxc <= 1'b0; else if(RxC_IRQ) irq_rxc <= #Tp 1'b1; else if(INT_SOURCE_Wr & DataIn[6]) irq_rxc <= #Tp 1'b0; end // Generating interrupt signal assign int_o = irq_txb & INT_MASKOut[0] | irq_txe & INT_MASKOut[1] | irq_rxb & INT_MASKOut[2] | irq_rxe & INT_MASKOut[3] | irq_busy & INT_MASKOut[4] | irq_txc & INT_MASKOut[5] | irq_rxc & INT_MASKOut[6] ; // For reading interrupt status assign INT_SOURCEOut = {26'h0, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb}; endmodule
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