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[/] [fat_32_file_parser/] [trunk/] [top_ps2keyboard.vhd] - Rev 2
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---------------------------------------------------------------------------------- -- Company: -- Engineer: CW -- -- Create Date: 21:25:31 10/06/2014 -- Design Name: -- Module Name: hw_client - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.CommonPckg.all; use work.SdCardPckg.all; library UNISIM; use UNISIM.VComponents.all; entity hw_client is Port ( CLK_IN : in STD_LOGIC; -- DEBUG Signals LED_OUT : out STD_LOGIC_VECTOR (7 downto 0); SSEG_OUT : out STD_LOGIC_VECTOR (7 downto 0); AN_OUT : out STD_LOGIC_VECTOR (3 downto 0); SW_IN : in STD_LOGIC_VECTOR (7 downto 0); BUTTON_IN : in STD_LOGIC_VECTOR (3 downto 0); vgaRed : out STD_LOGIC_VECTOR (2 downto 0); vgaGreen : out STD_LOGIC_VECTOR (2 downto 0); vgaBlue : out STD_LOGIC_VECTOR (1 downto 0); Hsync : out STD_LOGIC; Vsync : out STD_LOGIC; -- SD Signals SD_PRESENT_BAR_IN : in STD_LOGIC; SD_MOSI_OUT : out STD_LOGIC; SD_MISO_IN : in STD_LOGIC; SD_CLK_OUT : out STD_LOGIC; SD_CS_OUT : out STD_LOGIC); end hw_client; architecture Behavioral of hw_client is COMPONENT clk_mod Port ( CLK_50MHz_IN : in STD_LOGIC; CLK_25Mhz_OUT : out STD_LOGIC); END COMPONENT; COMPONENT sseg PORT ( CLK : in STD_LOGIC; VAL_IN : in STD_LOGIC_VECTOR (15 downto 0); SSEG_OUT : out STD_LOGIC_VECTOR(7 downto 0); AN_OUT : out STD_LOGIC_VECTOR(3 downto 0)); END COMPONENT; COMPONENT SdCardInit Port ( CLK_IN : in STD_LOGIC; RESET_IN : in STD_LOGIC; SD_PRESENT_BAR_IN : in STD_LOGIC; SD_INIT_OUT : out STD_LOGIC; SD_BLOCK_RD_OUT : out STD_LOGIC; SD_BLOCK_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); SD_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); SD_BUSY_IN : in STD_LOGIC; SD_BYTE_RD_OUT : out STD_LOGIC; SD_BYTE_RD_ACK_IN : in STD_LOGIC; SD_ERROR_IN : in STD_LOGIC_VECTOR (15 downto 0); SD_INIT_CMPLT_OUT : out STD_LOGIC; FAT_BEGIN_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); SECTORS_PER_FAT_OUT : out STD_LOGIC_VECTOR (31 downto 0); CLUSTER_BEGIN_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); SECTORS_PER_CLUSTER_OUT : out STD_LOGIC_VECTOR (7 downto 0); ROOT_DIR_FIRST_CLUSTER_OUT : out STD_LOGIC_VECTOR (31 downto 0)); END COMPONENT; COMPONENT SdCardReadWrite Port ( CLK_IN : in STD_LOGIC; RESET_IN : in STD_LOGIC; FAT_BEGIN_ADDR_IN : in STD_LOGIC_VECTOR (31 downto 0); SECTORS_PER_FAT_IN : in STD_LOGIC_VECTOR (31 downto 0); CLUSTER_BEGIN_ADDR_IN : in STD_LOGIC_VECTOR (31 downto 0); SECTORS_PER_CLUSTER_IN : in STD_LOGIC_VECTOR (7 downto 0); ROOT_DIR_FIRST_CLUSTER_IN : in STD_LOGIC_VECTOR (31 downto 0); SD_INIT_CMPLT_IN : in STD_LOGIC; SD_BLOCK_RD_OUT : out STD_LOGIC; SD_BLOCK_ADDR_OUT : out STD_LOGIC_VECTOR (31 downto 0); SD_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0); SD_BUSY_IN : in STD_LOGIC; SD_BYTE_RD_OUT : out STD_LOGIC; SD_BYTE_RD_ACK_IN : in STD_LOGIC; GET_NEXT_DIRENT_IN : in STD_LOGIC; NEXT_DIRENT_DONE_OUT : out STD_LOGIC; DIRENT_IS_FOLDER_OUT : out STD_LOGIC; RD_DIRENT_NAME_CHAR_IN : in STD_LOGIC; DIRENT_CHAR_OUT : out STD_LOGIC_VECTOR(7 downto 0); END_OF_DIRENT_NAME_OUT : out STD_LOGIC; NO_MORE_DIRENTS_OUT : out STD_LOGIC; DEBUG_IN : in STD_LOGIC_VECTOR(7 downto 0); DEBUG_OUT : out STD_LOGIC_VECTOR(15 downto 0); DEBUG_OUT2 : out STD_LOGIC_VECTOR(7 downto 0)); END COMPONENT; COMPONENT SdCardCtrl generic ( FREQ_G : real := 100.0; -- Master clock frequency (MHz). INIT_SPI_FREQ_G : real := 0.4; -- Slow SPI clock freq. during initialization (MHz). SPI_FREQ_G : real := 25.0; -- Operational SPI freq. to the SD card (MHz). BLOCK_SIZE_G : natural := 512; -- Number of bytes in an SD card block or sector. CARD_TYPE_G : CardType_t := SD_CARD_E -- Type of SD card connected to this controller. ); port ( -- Host-side interface signals. clk_i : in std_logic; -- Master clock. reset_i : in std_logic := NO; -- active-high, synchronous reset. rd_i : in std_logic := NO; -- active-high read block request. wr_i : in std_logic := NO; -- active-high write block request. continue_i : in std_logic := NO; -- If true, inc address and continue R/W. addr_i : in std_logic_vector(31 downto 0) := x"00000000"; -- Block address. data_i : in std_logic_vector(7 downto 0) := x"00"; -- Data to write to block. data_o : out std_logic_vector(7 downto 0) := x"00"; -- Data read from block. busy_o : out std_logic; -- High when controller is busy performing some operation. hndShk_i : in std_logic; -- High when host has data to give or has taken data. hndShk_o : out std_logic; -- High when controller has taken data or has data to give. error_o : out std_logic_vector(15 downto 0) := (others => NO); -- I/O signals to the external SD card. cs_bo : out std_logic := HI; -- Active-low chip-select. sclk_o : out std_logic := LO; -- Serial clock to SD card. mosi_o : out std_logic := HI; -- Serial data output to SD card. miso_i : in std_logic := ZERO; -- Serial data input from SD card. state_debug_o : out std_logic_vector(4 downto 0) ); END COMPONENT; COMPONENT vga80x40 PORT ( reset : in std_logic; clk25MHz : in std_logic; TEXT_A : out std_logic_vector(11 downto 0); TEXT_D : in std_logic_vector(7 downto 0); FONT_A : out std_logic_vector(11 downto 0); FONT_D : in std_logic_vector(7 downto 0); -- ocrx : in std_logic_vector(7 downto 0); ocry : in std_logic_vector(7 downto 0); octl : in std_logic_vector(7 downto 0); -- R : out std_logic; G : out std_logic; B : out std_logic; hsync : out std_logic; vsync : out std_logic); END COMPONENT; COMPONENT FONT_MEM PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT; COMPONENT TDP_RAM Generic (G_DATA_A_SIZE :natural :=32; G_ADDR_A_SIZE :natural :=9; G_RELATION :natural :=3; G_INIT_FILE :string :="");--log2(SIZE_A/SIZE_B) Port ( CLK_A_IN : in STD_LOGIC; WE_A_IN : in STD_LOGIC; ADDR_A_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE-1 downto 0); DATA_A_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); DATA_A_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE-1 downto 0); CLK_B_IN : in STD_LOGIC; WE_B_IN : in STD_LOGIC; ADDR_B_IN : in STD_LOGIC_VECTOR (G_ADDR_A_SIZE+G_RELATION-1 downto 0); DATA_B_IN : in STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0); DATA_B_OUT : out STD_LOGIC_VECTOR (G_DATA_A_SIZE/(2**G_RELATION)-1 downto 0)); END COMPONENT; subtype slv is std_logic_vector; signal clk_25MHz : std_logic; -------------------------- DEBUG ------------------------------------ signal sseg_data : std_logic_vector(15 downto 0) := (others => '0'); signal leds, switches : std_logic_vector(7 downto 0) := (others => '0'); signal debug_in, debug_out2 : std_logic_vector(7 downto 0) := (others => '0'); signal debug_out : std_logic_vector(15 downto 0) := (others => '0'); signal buttons, buttons_prev, buttons_edge : std_logic_vector(3 downto 0) := (others => '0'); signal debounce_count : unsigned(15 downto 0) := (others => '0'); signal repeat_count : unsigned(21 downto 0) := (others => '0'); signal debug_we : std_logic := '0'; signal debug_wr_data : std_logic_vector(7 downto 0) := (others => '0'); signal r, g, b : std_logic := '0'; signal font_addr, debug_addr : std_logic_vector(11 downto 0); signal font_data, debug_data : std_logic_vector(7 downto 0); signal debug_wr_addr : unsigned(11 downto 0) := (others => '0'); ------------------------ SD CARD SIGNALS ------------------------------- signal sd_mosi, sd_miso, sd_cs, sd_clk, sd_init_cmplt : std_logic; signal sd_busy, sd_present, sd_init, sd_rd_block, sd_rd_block_init_proc : std_logic := '0'; signal sd_rd_block_rd_proc, rd_byte, rd_byte_init_proc, rd_byte_rd_proc, rd_byte_ack : std_logic := '0'; signal sd_init_attempts_counter : unsigned(3 downto 0) := X"0"; signal sd_error : std_logic_vector(15 downto 0) := (others => '0'); signal sd_data, block_rd_data : std_logic_vector(7 downto 0) := (others => '0'); signal sd_block_addr, sd_block_addr_init_proc, sd_block_addr_rd_proc : std_logic_vector(31 downto 0) := (others => '0'); signal sectors_per_cluster : std_logic_vector(7 downto 0); signal fat_begin_lba, cluster_begin_lba : std_logic_vector(31 downto 0); signal sectors_per_fat, root_dir_cluster : std_logic_vector(31 downto 0); signal read_dirent_name, dirent_found, rd_dirent_char, end_of_dirent_name : std_logic := '0'; signal dirent_is_folder, no_more_dirents : std_logic := '0'; begin clk_mod_Inst : clk_mod PORT MAP ( CLK_50MHz_IN => CLK_IN, CLK_25Mhz_OUT => clk_25MHz); ----------------------- DEBUG I/O ---------------------------------- LED_OUT <= leds; switches <= SW_IN; sseg_inst : sseg PORT MAP ( CLK => clk_25MHz, VAL_IN => sseg_data, SSEG_OUT => SSEG_OUT, AN_OUT => AN_OUT); process(clk_25MHz) begin if rising_edge(clk_25MHz) then leds(7 downto 0) <= debug_out2(7 downto 0); --leds(6) <= sd_init_cmplt; --leds(7) <= not(SD_PRESENT_BAR_IN); end if; end process; debug_in <= "0000000"&buttons(1); sseg_data <= debug_out; --sseg_data <= sd_error; process(clk_25MHz) begin if rising_edge(clk_25MHz) then repeat_count <= repeat_count + 1; debounce_count <= debounce_count + 1; buttons_prev <= buttons; if debounce_count = X"0000" then buttons <= BUTTON_IN; end if; if buttons_prev(0) = '0' and buttons(0) = '1' then buttons_edge(0) <= '1'; elsif repeat_count = X"00000"&"00" and buttons(0) = '1' then buttons_edge(0) <= '1'; else buttons_edge(0) <= '0'; end if; if buttons_prev(1) = '0' and buttons(1) = '1' then buttons_edge(1) <= '1'; else buttons_edge(1) <= '0'; end if; if buttons_prev(3) = '0' and buttons(3) = '1' then buttons_edge(3) <= '1'; else buttons_edge(3) <= '0'; end if; end if; end process; vgaRed <= r&r&r; vgaGreen <= g&g&g; vgaBlue <= b&b; vga80x40_inst : vga80x40 PORT MAP ( reset => '0', clk25MHz => clk_25MHz, TEXT_A => debug_addr, TEXT_D => debug_data, FONT_A => font_addr, FONT_D => font_data, ocrx => X"00", ocry => X"00", octl => "11100111", R => r, G => g, B => b, hsync => Hsync, vsync => Vsync); Font_Mem_inst : FONT_MEM PORT MAP ( clka => clk_25MHz, wea => "0", addra => font_addr, dina => (others => '0'), douta => font_data); rd_dirent_char <= read_dirent_name; process(clk_25MHz) begin if rising_edge(clk_25MHz) then -- if dirent_found = '1' then -- leds(6) <= dirent_is_folder; -- end if; if dirent_found = '1' then read_dirent_name <= '1'; elsif end_of_dirent_name = '1' then read_dirent_name <= '0'; end if; if read_dirent_name = '1' then debug_we <= '1'; elsif end_of_dirent_name = '1' then debug_we <= '0'; end if; if read_dirent_name = '1' then if debug_wr_addr = X"C80" then debug_wr_addr <= (others => '0'); else debug_wr_addr <= debug_wr_addr + 1; end if; end if; end if; end process; debug_buf : TDP_RAM Generic Map ( G_DATA_A_SIZE => debug_data'length, G_ADDR_A_SIZE => debug_addr'length, G_RELATION => 0, --log2(SIZE_A/SIZE_B) G_INIT_FILE => "./coe_dir/ascii_space.coe") Port Map ( CLK_A_IN => clk_25MHz, WE_A_IN => '0', ADDR_A_IN => debug_addr, DATA_A_IN => X"00", DATA_A_OUT => debug_data, CLK_B_IN => clk_25MHz, WE_B_IN => debug_we, ADDR_B_IN => slv(debug_wr_addr), DATA_B_IN => debug_wr_data, DATA_B_OUT => open); --------------------------------------------------------- SD_CS_OUT <= sd_cs; SD_CLK_OUT <= sd_clk; SD_MOSI_OUT <= sd_mosi; sd_miso <= SD_MISO_IN; SdCardCtrl_Inst : SdCardCtrl generic map ( FREQ_G => 25.0, -- Master clock frequency (MHz). INIT_SPI_FREQ_G => 0.4, -- Slow SPI clock freq. during initialization (MHz). SPI_FREQ_G => 5.0, -- Operational SPI freq. to the SD card (MHz). BLOCK_SIZE_G => 512, -- Number of bytes in an SD card block or sector. CARD_TYPE_G => SD_CARD_E -- Type of SD card connected to this controller. ) port map ( -- Host-side interface signals. clk_i => clk_25MHz, reset_i => sd_init, rd_i => sd_rd_block, wr_i => '0', continue_i => '0', addr_i => sd_block_addr, data_i => X"00", data_o => sd_data, busy_o => sd_busy, hndShk_i => rd_byte, hndShk_o => rd_byte_ack, error_o => sd_error, -- I/O signals to the external SD card. cs_bo => sd_cs, sclk_o => sd_clk, mosi_o => sd_mosi, miso_i => sd_miso, state_debug_o => open); --leds(4 downto 0)); with sd_init_cmplt select rd_byte <= rd_byte_init_proc when '0', rd_byte_rd_proc when others; with sd_init_cmplt select sd_rd_block <= sd_rd_block_init_proc when '0', sd_rd_block_rd_proc when others; with sd_init_cmplt select sd_block_addr <= sd_block_addr_init_proc when '0', sd_block_addr_rd_proc when others; SdCardInit_Inst : SdCardInit Port Map( CLK_IN => clk_25MHz, RESET_IN => buttons_edge(3), SD_PRESENT_BAR_IN => SD_PRESENT_BAR_IN, SD_INIT_OUT => sd_init, SD_BLOCK_RD_OUT => sd_rd_block_init_proc, SD_BLOCK_ADDR_OUT => sd_block_addr_init_proc, SD_DATA_IN => sd_data, SD_BUSY_IN => sd_busy, SD_BYTE_RD_OUT => rd_byte_init_proc, SD_BYTE_RD_ACK_IN => rd_byte_ack, SD_ERROR_IN => sd_error, SD_INIT_CMPLT_OUT => sd_init_cmplt, FAT_BEGIN_ADDR_OUT => fat_begin_lba, SECTORS_PER_FAT_OUT => sectors_per_fat, CLUSTER_BEGIN_ADDR_OUT => cluster_begin_lba, SECTORS_PER_CLUSTER_OUT => sectors_per_cluster, ROOT_DIR_FIRST_CLUSTER_OUT => root_dir_cluster); SdCardReadWrite_Inst : SdCardReadWrite Port Map( CLK_IN => clk_25MHz, RESET_IN => buttons_edge(3), FAT_BEGIN_ADDR_IN => fat_begin_lba, SECTORS_PER_FAT_IN => sectors_per_fat, CLUSTER_BEGIN_ADDR_IN => cluster_begin_lba, SECTORS_PER_CLUSTER_IN => sectors_per_cluster, ROOT_DIR_FIRST_CLUSTER_IN => root_dir_cluster, SD_INIT_CMPLT_IN => sd_init_cmplt, SD_BLOCK_RD_OUT => sd_rd_block_rd_proc, SD_BLOCK_ADDR_OUT => sd_block_addr_rd_proc, SD_DATA_IN => sd_data, SD_BUSY_IN => sd_busy, SD_BYTE_RD_OUT => rd_byte_rd_proc, SD_BYTE_RD_ACK_IN => rd_byte_ack, GET_NEXT_DIRENT_IN => buttons_edge(0), NEXT_DIRENT_DONE_OUT => dirent_found, DIRENT_IS_FOLDER_OUT => dirent_is_folder, RD_DIRENT_NAME_CHAR_IN => rd_dirent_char, DIRENT_CHAR_OUT => debug_wr_data, END_OF_DIRENT_NAME_OUT => end_of_dirent_name, NO_MORE_DIRENTS_OUT => no_more_dirents, DEBUG_IN => debug_in, DEBUG_OUT => debug_out, DEBUG_OUT2 => debug_out2); end Behavioral;