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[/] [gecko3/] [trunk/] [GECKO3COM/] [gecko3com-ip/] [core/] [coregenerator/] [coregenerator_fifo_dualclock.xise] - Rev 25
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="coregenerator_fifo_dualclock.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator_fifo_dualclock.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="coregenerator_fifo_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="coregenerator_fifo_dualclock_padded.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation"/>
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</files>
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<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1500"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="Editor" xil_pn:value="Custom"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|coregenerator_fifo_dualclock"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/coregenerator_fifo_dualclock"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="coregenerator_fifo_dualclock"/>
<property xil_pn:name="Package" xil_pn:value="fg676"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
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<bindings/>
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<partitions>
<partition xil_pn:name="/coregenerator_fifo_dualclock"/>
</partitions>
</project>
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