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-- VHDL data flow description generated from `kontrol_utama_invmul`
--              date : Tue Jul 31 22:47:57 2001


-- Entity Declaration

ENTITY kontrol_utama_invmul IS
  PORT (
  start : in BIT;       -- start
  clk : in BIT; -- clk
  rst : in BIT; -- rst
  n_stage : in bit_vector(1 DOWNTO 0) ; -- n_stage
  n_iterasi : in bit_vector(3 DOWNTO 0) ;       -- n_iterasi
  n_dtin : in bit_vector(4 DOWNTO 0) ;  -- n_dtin
  n_dtout : in bit_vector(4 DOWNTO 0) ; -- n_dtout
  en_cstage : out BIT;  -- en_cstage
  c_cstage : out BIT;   -- c_cstage
  en_cite : out BIT;    -- en_cite
  c_cite : out BIT;     -- c_cite
  en_cdtin : out BIT;   -- en_cdtin
  c_cdtin : out BIT;    -- c_cdtin
  en_cdtout : out BIT;  -- en_cdtout
  c_cdtout : out BIT;   -- c_cdtout
  en_in : out BIT;      -- en_in
  en_out : out BIT;     -- en_out
  en_pipe : out BIT;    -- en_pipe
  sel : out BIT;        -- sel
  finish : out BIT;     -- finish
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END kontrol_utama_invmul;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF kontrol_utama_invmul IS
  SIGNAL current_state : REG_VECTOR(4 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL aux146 : BIT;          -- aux146
  SIGNAL aux145 : BIT;          -- aux145
  SIGNAL aux144 : BIT;          -- aux144
  SIGNAL aux135 : BIT;          -- aux135
  SIGNAL aux120 : BIT;          -- aux120
  SIGNAL aux116 : BIT;          -- aux116
  SIGNAL aux115 : BIT;          -- aux115
  SIGNAL aux111 : BIT;          -- aux111
  SIGNAL aux105 : BIT;          -- aux105
  SIGNAL aux103 : BIT;          -- aux103
  SIGNAL aux102 : BIT;          -- aux102
  SIGNAL aux101 : BIT;          -- aux101
  SIGNAL aux99 : BIT;           -- aux99
  SIGNAL aux98 : BIT;           -- aux98
  SIGNAL aux97 : BIT;           -- aux97
  SIGNAL aux96 : BIT;           -- aux96
  SIGNAL aux94 : BIT;           -- aux94
  SIGNAL aux93 : BIT;           -- aux93
  SIGNAL aux91 : BIT;           -- aux91
  SIGNAL aux90 : BIT;           -- aux90
  SIGNAL aux89 : BIT;           -- aux89
  SIGNAL aux87 : BIT;           -- aux87
  SIGNAL aux122 : BIT;          -- aux122
  SIGNAL aux124 : BIT;          -- aux124
  SIGNAL aux126 : BIT;          -- aux126
  SIGNAL aux127 : BIT;          -- aux127
  SIGNAL aux129 : BIT;          -- aux129

BEGIN
  aux129 <= (not (current_state (1)) and current_state (0));
  aux127 <= (not (current_state (0)) and not (current_state (2)));
  aux126 <= (not (current_state (2)) or not (current_state (0)));
  aux124 <= (not (rst) and not (current_state (3)) and aux122);
  aux122 <= (not (current_state (2)) and not (current_state (0)) and current_state
(4));
  aux87 <= (not (n_dtout (4)) or not (n_dtout (1)) or n_dtout (3) or n_dtout
(2) or n_dtout (0));
  aux89 <= (not (rst) and current_state (3));
  aux90 <= (not (current_state (0)) and aux89);
  aux91 <= (not (n_iterasi (3)) and not (n_iterasi (2)) and not (n_iterasi
(1)) and not (n_iterasi (0)));
  aux93 <= (start and (n_stage (1) or n_stage (0)) and aux91 and not (aux87));
  aux94 <= (not (current_state (3)) and not (rst));
  aux96 <= (not (rst) and current_state (1));
  aux97 <= (current_state (3) or (start and (n_stage (1) or n_stage (0)
or not (aux91)) and not (aux87)));
  aux98 <= (not (current_state (1)) and aux94);
  aux99 <= (current_state (0) and aux96);
  aux101 <= (not (n_dtout (3)) and not (n_dtout (2)) and not (n_dtout (0))
and start and n_iterasi (3) and n_iterasi (2) and n_iterasi
(1) and n_iterasi (0) and n_dtout (4) and n_dtout (1));
  aux102 <= (not (rst) and not (n_stage (1)) and not (n_stage (0)) and start
and aux91 and not (aux87));
  aux103 <= (not (n_stage (1)) or n_stage (0));
  aux105 <= (not (current_state (2)) and not (rst) and (current_state (0)
or (not (current_state (3)) and current_state (1))));
  aux111 <= (not (current_state (4)) and (aux96 or (not ((not (current_state
(0)) or current_state (2))) and aux94)));
  aux115 <= (not (current_state (3)) and not (rst) and aux103);
  aux116 <= (current_state (3) or current_state (1));
  aux120 <= (not (rst) and not (aux116) and not (aux103));
  aux135 <= (not (rst) and current_state (1) and aux122);
  aux144 <= (current_state (0) and not (rst) and aux116);
  aux145 <= not ((start and not (current_state (1)) and not (current_state
(0))));
  aux146 <= not ((not (current_state (3)) and (current_state (1) or aux103)));
  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED ((not (current_state (4)) and not (current_state (2)) and aux144)
or (not (rst) and ((current_state (4) and not (aux127)) or (not
(current_state (4)) and current_state (2) and (current_state
(0) or aux116)))) or (not (current_state (4)) and ((not (rst)
and not (aux127) and aux103) or (not (current_state (2)) and
not (current_state (0)) and aux120))) or (current_state (4)
and aux94 and (current_state (1) or aux93)));
  END BLOCK label0;
  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED ((not (current_state (2)) or current_state (4) or aux90 or aux99)
and (current_state (4) or current_state (2) or aux96 or (current_state
(0) and aux115)) and (not (current_state (4)) or (aux96 and
aux127) or (not (aux129) and aux89) or (aux127 and aux102)));
  END BLOCK label1;
  label2 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (2) <= GUARDED ((not (rst) or not (current_state (4))) and (not (current_state
(4)) or current_state (3) or current_state (2) or current_state
(1) or aux101) and ((current_state (4) and current_state (3)
and (current_state (2) or current_state (1))) or (not (current_state
(2)) and not (current_state (4)) and aux96) or (not (current_state
(4)) and aux144) or (not (current_state (0)) and (current_state
(4) or aux98))));
  END BLOCK label2;
  label3 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (3) <= GUARDED ((not (rst) and not (aux126)) or (not (rst) and current_state
(4) and not (aux129) and (current_state (3) or current_state
(2))) or (not (current_state (0)) and not (rst) and current_state
(4) and start and aux87) or (not (current_state (4)) and (not
(current_state (2)) or aux120) and (current_state (2) or aux89
or (not (rst) and aux129 and not (aux103)))));
  END BLOCK label3;
  label4 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (4) <= GUARDED ((not ((current_state (4) and aux94)) or (not (current_state
(2)) and aux145)) and (not ((not (rst) and not (current_state
(4)))) or (current_state (2) and (current_state (3) or current_state
(0))) or (not (current_state (2)) and not ((current_state (0)
or aux116))) or (current_state (0) and aux146)));
  END BLOCK label4;

finish <= ((not (current_state (2)) and not (current_state (4)) and aux90)
or (start and aux87 and aux124));

sel <= (aux135 or (not (current_state (4)) and aux126 and (aux96 or
(current_state (0) and aux94))) or (not (current_state (3))
and not (rst) and aux122 and aux93));

en_pipe <= ((current_state (2) and ((current_state (4) and aux94) or (not
(current_state (0)) and not (rst) and not (current_state (4)))))
or (not (current_state (4)) and (aux98 or (not (current_state
(2)) and aux99))) or (not (rst) and current_state (4) and aux127
and aux97));

en_out <= ((not (current_state (4)) and current_state (2) and (aux90 or
aux98)) or (aux124 and aux101));

en_in <= ((not (rst) and current_state (0) and not (current_state (2))
and not (current_state (4)) and (current_state (1) or (not (current_state
(3)) and aux103))) or (not (current_state (3)) and aux122 and
aux102));

c_cdtout <= (current_state (4) and aux105);

en_cdtout <= ((not (current_state (4)) and current_state (0) and aux89) or
(current_state (4) and current_state (2) and ((not (current_state
(1)) and aux89) or (current_state (0) and aux94))));

c_cdtin <= ((current_state (4) and not (aux129) and aux89) or aux111 or
(not (rst) and current_state (4) and aux127 and (current_state
(1) or aux93)));

en_cdtin <= ((current_state (4) and not (aux129) and aux89) or aux135 or
aux111 or (not (rst) and start and current_state (4) and aux127
and aux91 and not (aux87)));

c_cite <= (not (rst) and (current_state (3) or current_state (0)) and (not
(current_state (1)) or not (aux127)) and (current_state (4)
or (current_state (3) and aux129) or (current_state (2) and
not ((current_state (1) xor current_state (0))))));

en_cite <= ((not (current_state (4)) and ((current_state (2) and current_state
(1) and aux94) or not ((current_state (2) or not (aux98))) or
(not (rst) and (current_state (0) or (not (current_state (1))
and not (current_state (3)) and aux103))))) or (not (rst) and
current_state (4) and (current_state (2) or (not (current_state
(1)) and not (current_state (0)) and aux97))));

c_cstage <= ((current_state (4) or (current_state (0) and aux89) or (current_state
(2) and aux99)) and (not (current_state (4)) or (current_state
(2) and aux89) or aux105));

en_cstage <= ((not (current_state (0)) and current_state (4) and current_state
(2) and aux94) or (not (current_state (4)) and ((not (current_state
(1)) and aux115) or not (((aux126 or not (aux98)) and not ((not
(current_state (2)) and aux99)))))));
END;