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[/] [integer_square_root/] [tags/] [v2.0/] [src/] [mult_stage.sv] - Rev 7
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`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Yihua Liu
//
// Create Date: 2022/06/06 12:58:15
// Design Name:
// Module Name: mult_stage
// Project Name: lab_3_a
// Target Devices: xczu7eg-ffvf1517-2-i
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// This is one stage of an 8 stage (9 depending on how you look at it)
// pipelined multiplier that multiplies 2 64-bit integers and returns
// the low 64 bits of the result. This is not an ideal multiplier but
// is sufficient to allow a faster clock period than straight *
module mult_stage(
input clock, reset, start,
input [63:0] product_in, mplier_in, mcand_in,
output logic done,
output logic [63:0] product_out, mplier_out, mcand_out
);
// This parameter is used to change the number of stages.
// For example, if N_STAGE = 8, we are using an 8-stage pipelined multiplier.
parameter N_STAGE = 8;
logic [63:0] prod_in_reg, partial_prod_reg;
logic [63:0] partial_product, next_mplier, next_mcand;
assign product_out = prod_in_reg + partial_prod_reg;
assign partial_product = mplier_in[64/N_STAGE-1:0] * mcand_in;
// assign next_mplier = {{(64/N_STAGE){1'b0}},mplier_in[63:64/N_STAGE]};
// assign next_mcand = {mcand_in[64-64/N_STAGE-1:0],{(64/N_STAGE){1'b0}}};
assign next_mplier = mplier_in >> 64/N_STAGE;
assign next_mcand = mcand_in << 64/N_STAGE;
//synopsys sync_set_reset "reset"
always_ff @(posedge clock) begin
prod_in_reg <= #1 product_in;
partial_prod_reg <= #1 partial_product;
mplier_out <= #1 next_mplier;
mcand_out <= #1 next_mcand;
end
// synopsys sync_set_reset "reset"
always_ff @(posedge clock) begin
if(reset)
done <= #1 1'b0;
else
done <= #1 start;
end
endmodule