Light8080 CPU

Core Specifications

Written for publication on:

File name:	Light8080 Core Specifications

Version:	0.1

Creation Date:	03/12/12

Update Date:	03/12/12

Authors:	José A. Ruiz

Moti Litochevski

Table of Contents

1. Preface	4

1.1. Scope	4

1.2. Revision History	4

1.3. Abbreviations	4

2. Introduction	5

Synthesis results	6

3. CPU core Interface	7

Memory and I/O interface	8

Memory cycles	8

Opcode fetch cycles	9

I/O Cycles	10

Interrupts	11

Reset	12

4. Compatibility to original 8080	13

5. Instruction timing	14

Index of Tables

Table 1: Core Synthesis Results, VHDL version	6

Table 2: Core Synthesis Results, Verilog version	6

Table 3: CPU core interface description	9

Index of Figures

Figure 1: Memory Read Cycle	8

Figure 2: Memory Write Cycle	9

Figure 3: I/O Read Cycle	10

Figure 4: I/O Write Cycle	10

Preface

Scope

This document describes the IMA ADPCM Encoder & Decoder IP core operation, architecture and interfaces.

Revision History

Rev	Date	Author	Description
0,1	03/12/12	José A. Ruiz	First Draft

Abbreviations

ADPCM	Adaptive Differential Pulse Code Modulation
IMA	Interactive Multimedia Association

Introduction

The present document describes the interface of the Light8080 CPU core and gives brief usage instructions. Together with the demos and test benches provided with the project, the information provided in this document should be enough to use the core.

The OpenCores page for this project can be found here:

OpenCores project:	Lightweight 8080 compatible CPU :: OpenCores

This document will not cover anything that is already covered in the 8080 datasheets and manuals; namely, the opcode behavior, reset values for internal flags, etc.. Except for some details explained in section 5, the core is fully compatible with the original 8080 and thus original programming reference material can be used.

The project includes a 'design notes' document that explains briefly the architecture of the core and the format and behavior of the microcode. None of that information is necessary to use the core in an application so it has been omitted from this document.

This core has been designed to minimize area while supporting a decent clock rate. In order to reach that goal, the micromachine has been extremely simplified, with the result that instruction execution takes many more clock cycles than in the original 8080 – instruction execution times are compared in section 6.

Synthesis results

The following tables summarize the synthesis results of the bare CPU core (excluding any peripherals, program ROM or interrupt controller). The bare CPU is hardly useable without some support modules but the numbers given below should be a useful guide in estimating the size of a complete SOC core.

The VHDL version of the CPU includes only file light8080.vhdl. Synthesis results are given below.

Manufacturer	Family	Grade	Optimization	Elements Utilization	Fmax
Xilinx	Spartan 3	-5	Speed	209 LUTs + 1 BRAM	> 100 MHz
Xilinx	Spartan 2	-5	Speed	203 LUTs + 4 BRAMs	> 60 MHz
Altera	Cyclone II	C7	Balanced	413 LCs + 4 M4Ks	> 85 MHz

Table 1: Core Synthesis Results, VHDL version

The Verilog version of the CPU comprises two files, light8080.v and micro_rom.v. Synthesis results are given below and are nearly identical to the VHDL version, as would be expected from a RTL straight port.

Manufacturer	Family	Grade	Optimization	Elements Utilization	Fmax
Xilinx	Spartan 3	-5	Speed	209 LUTs + 1 BRAM	> 100MHz
Xilinx	Spartan 2	-5	Speed	203 LUTs + 4 BRAMs	> 60 MHz
Altera	Cyclone II	C7	Balanced	404 LCs + 4 M4Ks	> 80 MHz

Table 2: Core Synthesis Results, Verilog version

The above results where obtained using the following software versions:

Xilinx ISE 9.2i (App. Version J.36)

Altera Quartus II 9.0 build 235 SP 2

CPU core Interface

The following table summarizes the CPU core interface ports.

Name	Direction	Width	Description
clk	input	1	Global clock, active rising edge.
reset	input	1	Global core synchronous reset, active high.
addr_out	input	16	Address bus.
data_in	input	8	Input data bus.
data_out	output	8	Output data bus.
vma	output	1	Valid Memory Address, active when addr_out is valid.
io	output	1	Active high when access is I/O as opposed to memory.
rd	output	1	Active high for read cycles.
wr	output	1	Active high for write cycles.
fetch	output	1	Active high for read cycles
inta	output	1	Active high in interrupt acknowledge cycles.
inte	output	1	Active high when interrupts are enabled.
halt	output	1	Active high when the CPU is halted.
intr	input	1	Interrupt request input.

Table 3: CPU core interface description

All input signals are assumed to be synchronous to the master clock.

Since all these signals are meant to be internal to the FPGA, no effort has been made to characterize the setup and hold times for the inputs; and no synchronization logic is used at any of the inputs. The user should take care of this if any of the CPU inputs are to be driven from ouside the chip.

Memory and I/O interface

The memory interface is meant for connection to internal, synchronous BRAM.

Signal vma works as the synchronous master memory and io. More specifically:

All memory/io control signals (io,rd,wr) are valid only when vma is high. They never activate when vma is inactive.

Signals data_out and addr_out are only valid when vma='1'. The high address byte is 0x00 for all io accesses.

Signal data_in should be valid by the end of the cycle after vma='1', data is clocked in by the rising clock edge.

Memory cycles

These are the chronograms for the memory read and write cycles.

clk addr_out data_in vma rd wr io data_out address rd data Figure 1: Memory Read Cycle

clk addr_out data_in vma rd wr io data_out address wr data Figure 2: Memory Write Cycle

In the present version of the core there is no provision for wait states.

Opcode fetch cycles

An opcode fetch cycle is identical to a regular memory read cycle except signal fetch is asserted at the same time as signal vma.

When fetching multibyte instructions, signal fetch is asserted for the opcode fetch cycle only (the first cycle). Remember that the 8080 does not have any opcode longer than one byte, all extra bytes in multibyte instructions are operands.

I/O Cycles

I/O cycles are identical to memory cycles except for the assertion of signal io.

clk addr_out data_in vma rd wr io data_out address rd data Figure 3: I/O Read Cycle

clk addr_out data_in vma rd wr io data_out address wr data Figure 4: I/O Write Cycle

Like in the original 8080, the 8 most significant bits of the address bus in any I/O cycle are zero and the I/O port address is output in the lowest 8 bits.

Interrupts

The interrupt interface follows the behaviour of the original, with the exceptions mentioned below.

Signal inte reflects the state of the internal interrupt enable flag. Interrupts can be enabled or disabled under software control (instructions EI and DI), and are automatically disabled when an interrupt is acknowledged, as in the original 8080. Interrupts are enabled when inte is high.

Signal intr is sampled on all positive clock edges. If asserted when inte is high, interrupts will be disabled, inta will be asserted high and a fetch cycle will occur immediately after the current instruction ends execution, except if intr was asserted at the last cycle of an instruction. In that case it will be honored after the next instruction ends.

The special instruction fetch cycle that occurs when inta is high is called an interrupt acknowledge cycle.

The instruction fetched on the interrupt acknowledge cycle will be executed normally, except that PC will not be valid in any subsequent fetch cycles of the same instruction after the first (in multibyte instructions), and will not be autoincremented (In practice, the same as the original 8080).

Inta will remain high for the duration of the fetched instruction, including fetch and execution time (in the original 8080 it was asserted only for the opcode fetch cycle).

PC will not be autoincremented while inta is high, but it can be explicitly modified (that is, instructions like RST or CALL can be executed). Again, the same as the original.

Interrupts will be disabled upon assertion of inta, and remain disabled until explicitly enabled again by the program, usually with an EI instruction immedialely before the interrupt routine RET instruction (as in the original). Remember that EI does not enable interrupts until after the next instruction, as can be seen in the 80800 manual.

If intr is asserted when inte is low, the interrupt will not be attended but it will be registered in an internal int_pending flag, so it will be honored when interrupts are reenabled. The internal pending interrupt flag can't be cleared except by reset.
The above implies that any instruction can be supplied in an inta cycle, either single byte or multibyte. The original 8080 was subject to some limitations that don't apply to this core.

Like in the original 8080, the CPU relies on external logic to supply an interrupt vector (an instruction) at the interrupt acknowledge special fetch cycle. This instruction would usually be a single-byte RST but in principle it can be any instruction.

Supplying a multibyte instruction as an interrupt vector is somewhat difficult because the core does not provide any way to tell the second fetch cycle or the third – only the first is marked by the assertion of signal fetch. The external interrupt control logic must provide for this defficiency, which the original 8080 shares. Therefore the user is advised to use RST instructions as interrupt vectors.

Reset

Signal reset is synchronous and needs to be active for just 1 clock cycle. Once reset is deasserted, the first fetch at address 0x0000 will happen 4 cycles later.

Compatibility to original 8080

The core aims at full binary compatibility with the original 8080. The only known difference is the handling of flags CY and ACY by the logical instructions (OR, AND, XOR):

All logical instructions clear both flags CY and ACY, while the original 8080 doesn't. The original 8085 is too incompatible to the original 8080 in this regard.

It is not known to which extent this difference breaks compatibility to original 8080 code – particularly CP/M programs. At any rate, this difference will be removed in future non-alpha versions of the core, which will be 100% compatible to the original.

Instruction timing

The light8080 core is substantially slower than the original 8080 in clock cycles, as a consequence of the strong emphasis placed in area reduction. The following table gives execution times for all instructions in both the original CPU and this core.

Instruction	Intel 8080	Light8080	Instruction	Intel 8080	Light8080
MOV r1, r2	5	6	XRA r	4	6
MOV r, M	7	9	XRA M	7	9
MOV M, r	7	9	XRI data	7	9
MVI r, data	7	9	ORA r	4	6
MVI M, data	10	12	ORA M	7	9
LXI rp, data16	10	14	ORI data	7	9
LDA addr	13	16	CMP r	4	6
STA addr	13	16	CMP M	7	9
LHLD addr	16	19	CPI data	7	9
SHLD addr	16	19	RLC	4	5
LDAX rp	7	9	RRC	4	5
STAX rp	7	9	RAL	4	5
XCHG	4	16	RAR	4	5
ADD r	4	6	CMA	4	5
ADD M	7	9	CMC	4	5
ADI data	7	9	STC	4	5
ADC r	4	6	JMP	10	15
ADC M	7	9	Jcc	10	12/16
ACI data	7	9	CALL	17	29
SUB r	4	6	Ccc	11/17	12/30
SUB M	7	9	RET	10	14
SUI data	7	9	Rcc	5/11	5/15
SBB r	4	6	RST n	11	20
SBB M	7	9	PCHL	5	8
SBI data	7	9	PUSH rp	11	19
INR r	5	6	PUSH PSW	11	19
INR M	10	13	POP rp	10	14
INX rp	5	6	POP PSW	10	14
DCR r	5	6	XTHL	18	32
DCR M	10	14	SPHL	5	8
DCX rp	5	6	EI	4	5
DAD rp	10	8	DI	4	5
DAA	4	6	IN port	10	14
ANA r	4	6	OUT port	10	14
ANA M	7	9	HLT	7	5
ANI data	7	9	NOP	4	5