Subversion Repositories marca

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#               marca_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.



# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:01:50  OCTOBER 25, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name SMART_RECOMPILE ON

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY marca
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
set_global_assignment -name MUX_RESTRUCTURE ON

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C12Q240C8
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVCMOS

# Assembler Assignments
# =====================
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"

# Simulator Assignments
# =====================
set_global_assignment -name VECTOR_INPUT_SOURCE ..\\sim\\sim1.vwf
set_global_assignment -name SETUP_HOLD_DETECTION ON
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH OFF

# -------------------
# start ENTITY(marca)

# end ENTITY(marca)
# -----------------
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
set_global_assignment -name FMAX_REQUIREMENT "20 MHz"
set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
set_global_assignment -name FMAX_REQUIREMENT "20 MHz" -section_id dspio_clock
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION OFF -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name GLITCH_DETECTION OFF
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS ON
set_global_assignment -name REMOVE_DUPLICATE_LOGIC ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name IGNORE_CARRY_BUFFERS ON
set_global_assignment -name IGNORE_CASCADE_BUFFERS ON
set_global_assignment -name AUTO_RAM_RECOGNITION ON
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION ON
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE "MINIMIZE AREA WITH CHAINS"
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
set_global_assignment -name OPTIMIZE_TIMING OFF
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
set_global_assignment -name DO_COMBINED_ANALYSIS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "EXTRA EFFORT"
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name VHDL_INPUT_VERSION VHDL93
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_location_assignment PIN_152 -to clock
set_location_assignment PIN_153 -to ext_in[0]
set_location_assignment PIN_28 -to ext_in[1]
set_location_assignment PIN_178 -to ext_out[0]
set_location_assignment PIN_177 -to ext_out[1]
set_location_assignment PIN_42 -to ext_reset
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION AUTOMATICALLY
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION OFF
set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE ON
set_global_assignment -name SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION marca.saf
set_global_assignment -name POWER_USE_INPUT_FILES ON
set_global_assignment -name POWER_INPUT_FILE_NAME marca.saf -section_id marca.saf
set_global_assignment -name POWER_INPUT_FILE_TYPE SAF -section_id marca.saf
set_instance_assignment -name POWER_READ_INPUT_FILE marca.saf -to marca
set_global_assignment -name VHDL_FILE ../vhdl/marca_pkg.vhd
set_global_assignment -name VHDL_FILE ../vhdl/sc_pkg.vhd
set_global_assignment -name VHDL_FILE ../vhdl/code_memory.vhd
set_global_assignment -name VHDL_FILE ../vhdl/fetch_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/fetch.vhd
set_global_assignment -name VHDL_FILE ../vhdl/regfile_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/regfile.vhd
set_global_assignment -name VHDL_FILE ../vhdl/decode_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/decode.vhd
set_global_assignment -name VHDL_FILE ../vhdl/multiplier_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/multiplier.vhd
set_global_assignment -name VHDL_FILE ../vhdl/divider_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/divider.vhd
set_global_assignment -name VHDL_FILE ../vhdl/alu_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/alu.vhd
set_global_assignment -name VHDL_FILE ../vhdl/data_memory.vhd
set_global_assignment -name VHDL_FILE ../vhdl/data_rom.vhd
set_global_assignment -name VHDL_FILE ../vhdl/fifo.vhd
set_global_assignment -name VHDL_FILE ../vhdl/sc_uart.vhd
set_global_assignment -name VHDL_FILE ../vhdl/mem_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/mem.vhd
set_global_assignment -name VHDL_FILE ../vhdl/intr_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/intr.vhd
set_global_assignment -name VHDL_FILE ../vhdl/execute_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/execute.vhd
set_global_assignment -name VHDL_FILE ../vhdl/writeback_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/writeback.vhd
set_global_assignment -name VHDL_FILE ../vhdl/marca_ent.vhd
set_global_assignment -name VHDL_FILE ../vhdl/marca.vhd
set_global_assignment -name MIF_FILE ../vhdl/code.mif
set_global_assignment -name MIF_FILE ../vhdl/rom0.mif
set_global_assignment -name MIF_FILE ../vhdl/rom1.mif
set_global_assignment -name VECTOR_WAVEFORM_FILE ../sim/sim1.vwf
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS ON
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW ON