Release 3.1i - Par D.19

Sat May 04 18:33:07 2002

par -w -ol 2 -d 0 map.ncd uartimpl.ncd uartimpl.pcf

Constraints file: uartimpl.pcf

Loading device database for application par from file "map.ncd".
   "uartimpl" is an NCD, version 2.32, device xcs10, package tq144, speed -3
Loading device for application par from file '4005e.nph' in environment
C:/Fndtn.
Device speed data version:  x1_0.14.2.2 1.7 PRELIMINARY.

Device utilization summary:

   Number of External IOBs            28 out of 112    25%
      Flops:                           0
      Latches:                         0
   Number of IOBs driving Global Buffers    2 out of 8      25%

   Number of CLBs                     44 out of 196    22%
      Total CLB Flops:                63 out of 392    16%
      4 input LUTs:                   63 out of 392    16%
      3 input LUTs:                   20 out of 196    10%

   Number of PRI-CLKs                  2 out of 4      50%

Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)

Starting initial Placement phase.  REAL time: 0 secs 
Finished initial Placement phase.  REAL time: 0 secs 

Starting Constructive Placer.  REAL time: 0 secs 
Placer score = 68880
Placer score = 44100
Placer score = 35940
Placer score = 32580
Placer score = 28320
Placer score = 27540
Placer score = 26760
Placer score = 25740
Placer score = 25080
Placer score = 25020
Placer score = 24840
Placer score = 24600
Placer score = 24180
Placer score = 24060
Finished Constructive Placer.  REAL time: 2 secs 

Writing design to file "uartimpl.ncd".

Starting Optimizing Placer.  REAL time: 2 secs 
Optimizing  
Swapped 26 comps.
Xilinx Placer [1]   22320   REAL time: 2 secs 

Finished Optimizing Placer.  REAL time: 2 secs 

Writing design to file "uartimpl.ncd".

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 

0 connection(s) routed; 315 unrouted active, 3 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 2 secs 
Starting iterative routing. 
Routing active signals.
End of iteration 1 
315 successful; 0 unrouted active,
   3 unrouted PWR/GND; (0) REAL time: 3 secs 
End of iteration 2 
315 successful; 0 unrouted active,
   3 unrouted PWR/GND; (0) REAL time: 3 secs 
Constraints are met. 
Routing PWR/GND nets.
Power and ground nets completely routed. 
Writing design to file "uartimpl.ncd".
Starting cleanup 
Improving routing.
End of cleanup iteration 1 
318 successful; 0 unrouted; (0) REAL time: 4 secs 
Writing design to file "uartimpl.ncd".
Total REAL time: 4 secs 
Total CPU  time: 4 secs 
End of route.  318 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design

Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 306

The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        2.041 ns
   The Maximum Pin Delay is:                               9.391 ns
   The Average Connection Delay on the 10 Worst Nets is:   5.097 ns

   Listing Pin Delays by value: (ns)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 10.00  d >= 10.00
   ---------   ---------   ---------   ---------   ---------   ---------
         202          89          25           0           2           0

Writing design to file "uartimpl.ncd".

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 5 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.