Minimal OpenRISC System on Chip

How To

Download IP cores

download minsoc

download further necessary IP cores

cd minsoc/rtl/verilog

svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk adv_debug_sys

svn co http://opencores.org/ocsvn/ethmac/ethmac/trunk ethmac

svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1200 or1200

svn co http://opencores.org/ocsvn/uart16550/uart16550/trunk uart16550

Install GNU toolchain and adv_jtag_bridge

Follow: http://www.opencores.org/openrisc,gnu_toolchain (to install binutils, gcc, gdb)

To debug and load the firmware you have to use the new advanced_debug_system. This project is included in the minsoc files inside of minsoc/rtl/verilog/adv_debug_sys. There you can find the software in Software and the documentation, which shall help you to go under Doc.

change the Makefile in Software/adv_jtag_bridge and compile the software using make.

change Makefile line 34, “INCLUDE_JSP_SERVER=true” to “INCLUDE_JSP_SERVER=false”

make

sudo make install

Copy the description file of your FPGA to your home directory “cp /opt/Xilinx/10.1/ISE/spartan3e/data/xc3s500e_fg320.bsd ~/”

With the adv_jtag_bridge you can also debug your simulation. To do so, the simulation has to include a vpi module. This has to be compiled by your system. The sources are found under “minsoc/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus”.

cd minsoc/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus

make

cp minsoc_adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus/jp-io-vpi.vpi minsoc/bench/verilog/vpi

The adv_jtag_bridge connect the debug system to gdb, the GNU debugger. But the actual version of gdb has some issues, which have to be corrected before use. To do so, the adv_jtag_bridge software includes a patch for gdb. Save the patch to the gdb source code directory installed by the toolchain installation script and patch it:

cp minsoc/adv_debug_sys/Software/adv_jtag_bridge/gdb-6.8-bz436037-reg-no-longer-active.patch toolchain_build_directory/gdb-6.8

cd toolchain_build_directory/gdb-6.8

patch -p1 < gdb-6.8-bz436037-reg-no-longer-active.patch

make

sudo make install

Compile Software

edit sw/support/orp.ld line 14 LENGTH = 0x00006E00 to

your memory amount in Bytes, where MEMORYADRWIDTH is defined in `define MEMORY_ADR_WIDTH in “minsoc_defines.v”

minus ORIGIN = 0x00001200

(e.g. 4*2^13 = 32,768 Bytes = 0x8000 | LENGTH = 0x8000 – 0x1200 = 0x6E00)

select your STACK size on board.h line 16 #define STACK_SIZE 0x01000

change your IN_CLK if not using 25000000 (25MHz)

inside of sw/support make clean, make all

inside of sw/utils make clean, make all

inside of the target software (e.g. sw/uart) make clean, make all

Simulation

Install Icarus Verilog

You will need at least version 0.9.1 (ftp://ftp.icarus.com/pub/eda/verilog/v0.9/)

configure your system: minsoc_defines.v (not necessary)

Note: (since revision 17) Ethernet functionality of testbench does not base on eth_phy.v anymore. This means that you can uncomment ETHERNET on minsoc_defines.v and simulate it without simulation speed decrease and without changing any file.

Previous to revision 17: if you uncomment “`define ETHERNET” you have to:

edit “minsoc/sim/run/generate_bench”:

substitute “../bin/minsoc_model_fast.txt” for “../bin/minsoc_model_complete.txt”

THIS WILL SLOW DOWN YOUR SIMULATION BY FACTOR 300

configure minsoc_bench_defines.v (not necessary)

Your testbench will use a memory model, not actually the same memory controller the implementation uses. This enables the option “`define INITIALIZE_MEMORY_MODEL”, where the firmware is loaded to the memory before testbench start.

You may use the actual implementation memory:

comment “`define INITIALIZE_MEMORY_MODEL”

edit minsoc/sim/run/generate_bench

substitute “../bin/minsoc_model.txt” for “../bin/minsoc_memory.txt”

You might want to uncomment “`define START_UP”, it loads the firmware to a SPI memory. At start of testbench the system reads this memory and loads the firmware to main memory. Takes +-3 min. This is possible to be used for a real system, all you have to do is uncomment “`define START_UP” from minsoc/rtl/verilog/minsoc_defines.v.

Modify testbench (not necessary)

configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v

comment out line 67, “`define DBG_JSP_SUPPORTED”

command to start testbench and select firmware

from minsoc/sim/run/

./generate_bench

./run_bench <your_firmware.hex>

./run_bench ../../sw/uart/uart-nocache-twobyte-sizefirst.hex

Debuging the testbench (3 terminals)

terminal 1: from minsoc/sim/run/

./generate_bench

./run_bench <your_firmware.hex>

./run_bench ../../sw/uart/uart-nocache-twobyte-sizefirst.hex

terminal 2: from minsoc/sim/run

./start_server

terminal 3: at minsoc/sw/uart

or32-elf-gdb uart-nocache.or32

target remote :9999

load

if you have INITIALIZE_MEMORY_MODEL enabled you don't have to do this

if you have START_UP and waited for the message: “Memory start-up completed...” you also don't need this

set $pc=0x100

c

Implementation

configure minsoc_defines.v (recommended values for different devices under 7. Examples)

Select your FPGA device by uncommenting its manufacturer and commenting all other manufacturers. Select then your FPGA model by uncommenting it in case you have a Xilinx FPGA, for Altera comment all out.

`define MEMORY_ADR_WIDTH 13 defines the amount of memory you get. The depth is defined by , since its data width is 32 bits, the amount in Bytes is 4 times its depth. (this is not allowed to be less than 12, 11 is the memory block address width)

choose a clock division for your global clock related to your design max speed by changing the definition: "`define CLOCK_DIVISOR 5". If you have an Altera device please use only even numbers for the division, odd numbers are going to be rounded down.

Define your RESET polarity: uncomment "`define POSITIVE_RESET" for an active high reset or "`define NEGATIVE_RESET" for an active low reset and comment the other.

configure or1200_defines.v (optional -> reduce logic usage) (recommended values for different devices under 7. Examples)

Target FPGA memories (OR1200_XILINX_RAMB16 for Xilinx, Spartan 3 and above, OR1200_ALTERA_LPM for all Altera)

Type of register file RAM (generic, twoport or dual port) (dual port is supported by Xilinx BRAM and Altera)(select only one of the three)

If not using Linux you can comment out OR1200_QMEM_IMPLEMENTED.

configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v

comment out line 67, “`define DBG_JSP_SUPPORTED”

define user constrains for system pinout (edit backend/yourboard.ucf file)

create project in project manager (ISE, Quartus), include files

synthesize, P&R and upload bitfile

connect the cable to the selected JTAG TAP

Software Upload and Debugging

Upload software and debug for simulation and implementation using GDB

start adv_jtag_bridge

cd ~/

sudo adv_jtag_bridge xpc3 (xess, usbblaster, xpc_usb, ft2232)

Let the program running and open another terminal

Open a terminal program (e.g. gtkterm)

configure port to a serial port connected to your board

configure bitrate to 115200

start gdb, load firmware (example)

cd minsoc/sw/uart

or32-elf-gdb uart-nocache.or32

target remote :9999

load

set $pc=0x100

c

Inside of gtkterm “Hello World.” should have appeared, if you press any key inside of gtkterm the processor will return the next alphabetical letter (press a, it returns b)

Examples

Note: different constraint files for different boards → inside of backend directory

Spartan 3A DSP 1800 (100%)

minsoc_defines.v

no definitions change, ready to go

or1200_defines.v (optional, reduce logic use)

uncomment `define OR1200_XILINX_RAMB16

uncomment `define OR1200_RFRAM_DUALPORT

comment `define OR1200_RFRAM_GENERIC

Spartan 3E Starter Kit no Ethernet (100%)

minsoc_defines.v

comment `define SPARTAN3A

uncomment `define SPARTAN3E

change CLOCK_DIVISOR from 5 to 2

comment `define ETHERNET

or1200_defines.v

uncomment `define OR1200_XILINX_RAMB16

Spartan 3E Starter Kit with Ethernet (not tested)

Synthesis properties:

Optimization Goal: Area

Optimization Effort: High

minsoc_defines.v

comment `define SPARTAN3A

uncomment `define SPARTAN3E

let CLOCK_DIVISOR at 5

change MEMORY_ADR_WIDTH from 13 to 12

uncomment `define ETHERNET

comment `define UART

this is not necessary, though you will get 99% device usage if not commenting, 89% otherwise.

or1200_defines.v

uncomment `define OR1200_XILINX_RAMB16

comment `define OR1200_MULT_IMPLEMENTED

comment `define OR1200_MAC_IMPLEMENTED

uncomment `define OR1200_RFRAM_DUALPORT

comment `define OR1200_RFRAM_GENERIC

comment `define OR1200_PM_IMPLEMENTED

comment `define OR1200_QMEM_IMPLEMENTED

comment `define OR1200_CFGR_IMPLEMENTED

eth_defines.v

uncomment `define ETH_FIFO_XILINX

uncomment `define ETH_XILINX_RAMB4

Collateral effects:

from sw/support/Makefile.inc line 7:

GCC_OPT=-mhard-mul -g to GCC_OPT=-msoft-mul -g

change sw/support/orp.ld:

ram: LENGTH = from 0x00006E00 to 0x00002E00

this is not much memory, I recommend the inclusion of the wb_ddr project to minsoc to use your DDR SRAM memory

Further area optimization possibilities: (not necessary, DON'T DO)

Turn off: pic, tick timer or debug unit

Altera Devices

minsoc_defines.v

uncoment `define ALTERA_FPGA

comment `define XILINX_FPGA

comment `define SPARTAN3A

select your memory amount "`define MEMORY_ADR_WIDTH 13"

choose a clock division for your global clock related to your design max speed by changing the definition: "`define CLOCK_DIVISOR 5". Since you have an Altera device please use only even numbers for the division, odd numbers are going to be rounded down.

Define your RESET polarity uncommenting "`define POSITIVE_RESET" or "`define NEGATIVE_RESET" and commenting the other.

or1200_defines.v

uncomment `define OR1200_ALTERA_LPM

uncomment `define OR1200_RFRAM_DUALPORT

comment `define OR1200_RFRAM_GENERIC

comment `define OR1200_QMEM_IMPLEMENTED