Minimal OpenRISC System on Chip

How To

Compile Software

inside of sw/support make clean, make all

inside of sw/utils make clean, make all

inside of the target software (e.g. sw/uart) make clean, make all

Simulation

configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v

comment out line 67, “`define DBG_JSP_SUPPORTED”

command to start testbench and select firmware

from minsoc/sim/run/

./generate_bench

./run_bench <your_firmware.hex>

./run_bench ../../sw/uart/uart-nocache-twobyte-sizefirst.hex

Synthesis

configure minsoc/rtl/verilog/minsoc_defines.v (recommended values for different devices under synthesis_examples.pdf)

Select your FPGA device by uncommenting its manufacturer and commenting all other manufacturers. Select then your FPGA model by uncommenting it in case you have a Xilinx FPGA, for Altera comment all out.

`define MEMORY_ADR_WIDTH 13 defines the amount of memory you get. The depth is defined by , since its data width is 32 bits, the amount in Bytes is 4 times its depth. (this is not allowed to be less than 12, 11 is the memory block address width)

(if you change from 13, check FAQ->How to adapt the firmware to my implementation?)

choose a clock division for your global clock related to your design max speed by changing the definition: "`define CLOCK_DIVISOR 5". If you have an Altera device please use only even numbers for the division, odd numbers are going to be rounded down.

(if your resulting clock is not 25MHz, check FAQ->How to adapt the firmware to my implementation?)

Define your RESET polarity: uncomment "`define POSITIVE_RESET" for an active high reset or "`define NEGATIVE_RESET" for an active low reset and comment the other.

configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v

comment out line 67, “`define DBG_JSP_SUPPORTED”

define user constrains for system pinout (edit minsoc/backend/yourboard.ucf file)

create project in project manager (ISE, Quartus), include files

synthesize, P&R and upload bitfile

connect the cable to the selected JTAG TAP

Software Upload and Debugging

Upload software and debug for simulation and implementation using GDB

start adv_jtag_bridge

cd ~/

sudo adv_jtag_bridge xpc3 (xess, usbblaster, xpc_usb, ft2232)

Let the program running and open another terminal

Open a terminal program (e.g. gtkterm)

configure port to a serial port connected to your board

configure bitrate to 115200

start gdb, load firmware (example)

cd minsoc/sw/uart

or32-elf-gdb uart-nocache.or32

target remote :9999

load

set $pc=0x100

c

Inside of gtkterm “Hello World.” should have appeared, if you press any key inside of gtkterm the processor will return the next alphabetical letter (press a, it returns b)