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PROJECT_DIR=rtl/verilog/ethmac/rtl/verilog
PROJECT_SRC=(eth_cop.v
eth_registers.v
eth_rxethmac.v
eth_miim.v
ethmac.v
eth_rxaddrcheck.v
eth_outputcontrol.v
eth_rxstatem.v
eth_txethmac.v
eth_wishbone.v
eth_maccontrol.v
eth_txstatem.v
ethmac_defines.v
eth_spram_256x32.v
eth_shiftreg.v
eth_clockgen.v
eth_crc.v
eth_rxcounters.v
eth_macstatus.v
eth_random.v
eth_register.v
eth_fifo.v
eth_receivecontrol.v
eth_transmitcontrol.v
eth_txcounters.v)