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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [memctrl/] [sdctrl.in.help] - Rev 2
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SDRAM controller enable
CONFIG_SDCTRL
Say Y here to enabled a 32/64-bit PC133 SDRAM controller.
SDRAM controller inverted clock
CONFIG_SDCTRL_INVCLK
If you say Y here, the SDRAM clock will be inverted in respect to the
system clock and the SDRAM signals. This will limit the SDRAM frequency
to 50/66 MHz, but has the benefit that you will not need a PLL to
generate the SDRAM clock. On FPGA targets, say Y. On ASIC targets,
say N and tell your foundry to balance the SDRAM clock output.
64-bit data bus
CONFIG_SDCTRL_BUS64
Say Y here to enable 64-bit data bus.
Page burst enable
CONFIG_SDCTRL_PAGE
Say Y here to enable SDRAM page burst operation. This will implement
read operations using page bursts rather than 8-word bursts and save
about 500 gates (100 LUTs). Note that not all SDRAM supports page
burst, so use this option with care.
Programmable page burst enable
CONFIG_SDCTRL_PROGPAGE
Say Y here to enable programmable SDRAM page burst operation. This
will allow to dynamically enable/disable page burst by setting
bit 17 in MCFG2.