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[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [system.mhs] - Rev 6
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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
# Fri Jun 22 12:14:26 2007
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -7
# Processor: PPC 405
# Processor clock frequency: 100.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory : 128 KB
# Total Off Chip Memory : 512 MB
# - DDR_SDRAM_64Mx64 Dual Rank = 256 MB
# - DDR_512MB_64Mx64_rank2_row13_col10_cl2_5 = 256 MB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk, DIR = O, VEC = [0:2]
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn, DIR = O, VEC = [0:2]
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr, DIR = O, VEC = [0:12]
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr, DIR = O, VEC = [0:1]
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn, DIR = O
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn, DIR = O
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn, DIR = O
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM, DIR = O, VEC = [0:7]
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS, DIR = IO, VEC = [0:7]
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ, DIR = IO, VEC = [0:63]
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE, DIR = O, VEC = [0:1]
PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn, DIR = O, VEC = [0:1]
PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = O
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT myipif_0_LEDs_pin = myipif_0_LEDs, DIR = O, VEC = [3:0]
PORT myipif_0_VGA_OUT_PIXEL_CLOCK_pin = myipif_0_VGA_OUT_PIXEL_CLOCK, DIR = O
PORT myipif_0_VGA_COMP_SYNCH_pin = myipif_0_VGA_COMP_SYNCH, DIR = O
PORT myipif_0_VGA_OUT_BLANK_Z_pin = myipif_0_VGA_OUT_BLANK_Z, DIR = O
PORT myipif_0_VGA_HSYNCH_pin = myipif_0_VGA_HSYNCH, DIR = O
PORT myipif_0_VGA_VSYNCH_pin = myipif_0_VGA_VSYNCH, DIR = O
PORT myipif_0_VGA_OUT_RED_pin = myipif_0_VGA_OUT_RED, DIR = O, VEC = [7:0]
PORT myipif_0_VGA_OUT_GREEN_pin = myipif_0_VGA_OUT_GREEN, DIR = O, VEC = [7:0]
PORT myipif_0_VGA_OUT_BLUE_pin = myipif_0_VGA_OUT_BLUE, DIR = O, VEC = [7:0]
PORT myipif_0_SWITCHEs_pin = myipif_0_SWITCHEs, DIR = I, VEC = [3:0]
PORT myipif_0_BUTTONs_pin = myipif_0_BUTTONs, DIR = I, VEC = [4:0]
BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE IPLB = plb
BUS_INTERFACE DPLB = plb
BUS_INTERFACE JTAGPPC = jtagppc_0_JTAGPPC0
PORT PLBCLK = sys_clk_s
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT CPMC405CLOCK = sys_clk_s
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE JTAGPPC0 = jtagppc_0_JTAGPPC0
BUS_INTERFACE JTAGPPC1 = jtagppc_0_JTAGPPC1
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_block
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Ext_Reset_In = sys_rst_s
PORT Slowest_sync_clk = sys_clk_s
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
PORT Core_Reset_Req = C405RSTCORERESETREQ
PORT System_Reset_Req = C405RSTSYSRESETREQ
PORT Rstc405resetchip = RSTC405RESETCHIP
PORT Rstc405resetcore = RSTC405RESETCORE
PORT Rstc405resetsys = RSTC405RESETSYS
PORT Bus_Struct_Reset = sys_bus_reset
PORT Dcm_locked = dcm_1_lock
END
BEGIN plb_v34
PARAMETER INSTANCE = plb
PARAMETER HW_VER = 1.02.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = sys_clk_s
END
BEGIN opb_v20
PARAMETER INSTANCE = opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT OPB_Clk = sys_clk_s
END
BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
PARAMETER HW_VER = 1.01.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_NUM_ADDR_RNG = 1
PARAMETER C_RNG0_BASEADDR = 0x00000000
PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
BUS_INTERFACE MOPB = opb
BUS_INTERFACE SPLB = plb
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = opb
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END
BEGIN opb_ddr
PARAMETER INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
PARAMETER HW_VER = 2.00.c
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_NUM_BANKS_MEM = 2
PARAMETER C_NUM_CLK_PAIRS = 4
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_TMRD = 20000
PARAMETER C_DDR_TWR = 20000
PARAMETER C_DDR_TRAS = 60000
PARAMETER C_DDR_TRC = 90000
PARAMETER C_DDR_TRFC = 100000
PARAMETER C_DDR_TRCD = 30000
PARAMETER C_DDR_TRRD = 20000
PARAMETER C_DDR_TRP = 30000
PARAMETER C_DDR_TREFC = 70300000
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 10
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_DDR_DWIDTH = 64
PARAMETER C_MEM0_BASEADDR = 0x00000000
PARAMETER C_MEM0_HIGHADDR = 0x0fffffff
PARAMETER C_MEM1_BASEADDR = 0x10000000
PARAMETER C_MEM1_HIGHADDR = 0x1fffffff
PARAMETER C_INCLUDE_BURST_SUPPORT = 1
BUS_INTERFACE SOPB = opb
PORT DDR_Addr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr
PORT DDR_CASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn
PORT DDR_CKE = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE
PORT DDR_CSn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn
PORT DDR_RASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn
PORT DDR_WEn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn
PORT DDR_DM = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM
PORT DDR_DQS = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ
PORT DDR_Clk = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
PORT DDR_Clkn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn & 0b0
PORT Device_Clk90_in = clk_90_s
PORT Device_Clk90_in_n = clk_90_n_s
PORT Device_Clk = sys_clk_s
PORT Device_Clk_n = sys_clk_n_s
PORT DDR_Clk90_in = ddr_clk_90_s
PORT DDR_Clk90_in_n = ddr_clk_90_n_s
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_plb_clk_period_ps = 10000
PARAMETER c_baseaddr = 0xfffe0000
PARAMETER c_highaddr = 0xffffffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END
BEGIN util_vector_logic
PARAMETER INSTANCE = sysclk_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = sys_clk_s
PORT Res = sys_clk_n_s
END
BEGIN util_vector_logic
PARAMETER INSTANCE = clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = clk_90_s
PORT Res = clk_90_n_s
END
BEGIN util_vector_logic
PARAMETER INSTANCE = ddr_clk90_inv
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE = 1
PARAMETER C_OPERATION = not
PORT Op1 = ddr_clk_90_s
PORT Res = ddr_clk_90_n_s
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLK90 = clk_90_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLK90_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_PHASE_SHIFT = 60
PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
PARAMETER C_EXT_RESET_HIGH = 0
PORT CLKIN = ddr_feedback_s
PORT CLK90 = ddr_clk_90_s
PORT CLK0 = dcm_1_FB
PORT CLKFB = dcm_1_FB
PORT RST = dcm_0_lock
PORT LOCKED = dcm_1_lock
END
BEGIN myipif
PARAMETER INSTANCE = myipif_0
PARAMETER C_BASEADDR = 0x50000000
PARAMETER C_HIGHADDR = 0x5000FFFF
BUS_INTERFACE MSOPB = opb
PORT LEDs = myipif_0_LEDs
PORT BUTTONs = myipif_0_BUTTONs
PORT SWITCHEs = myipif_0_SWITCHEs
PORT VGA_OUT_PIXEL_CLOCK = myipif_0_VGA_OUT_PIXEL_CLOCK
PORT VGA_COMP_SYNCH = myipif_0_VGA_COMP_SYNCH
PORT VGA_OUT_BLANK_Z = myipif_0_VGA_OUT_BLANK_Z
PORT VGA_HSYNCH = myipif_0_VGA_HSYNCH
PORT VGA_VSYNCH = myipif_0_VGA_VSYNCH
PORT VGA_OUT_RED = myipif_0_VGA_OUT_RED
PORT VGA_OUT_GREEN = myipif_0_VGA_OUT_GREEN
PORT VGA_OUT_BLUE = myipif_0_VGA_OUT_BLUE
END
BEGIN ppc405
PARAMETER INSTANCE = ppc405_1
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_JTAGPPC1
END
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