Renesas / SuperH SH Dependent Features
**************************************

Options
=======

AS has following command-line options for the Renesas (formerly Hitachi) / SuperH SH family.

--little
     Generate little endian code.

--big
     Generate big endian code.

--relax
     Alter jump instructions for long displacements.

--small
     Align sections to 4 byte boundaries, not 16.

--dsp
     Enable sh-dsp insns, and disable sh3e / sh4 insns.

--renesas
     Disable optimization with section symbol for compatibility with Renesas assembler.

--allow-reg-prefix
     Allow '$' as a register name prefix.

--fdpic
     Generate an FDPIC object file.

--isa=sh4 | sh4a
     Specify the sh4 or sh4a instruction set.

--isa=dsp
     Enable sh-dsp insns, and disable sh3e / sh4 insns.

--isa=fp
     Enable sh2e, sh3e, sh4, and sh4a insn sets.

--isa=all
     Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets.

-h-tick-hex
     Support H'00 style hex constants in addition to 0x00 style.

Syntax
======

Special Characters
------------------

! is the line comment character.

You can use ; instead of a newline to separate statements.

If a # appears as the first character of a line then the whole line is treated as a comment, but in this case the line could also be a logical line number directive (see Comments) or a preprocessor control command (see Preprocessing).

Since $ has no special meaning, you may use it in symbol names.

Register Names
--------------

You can use the predefined symbols r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, and r15 to refer to the SH registers.

The SH also has these control registers:

pr
     procedure register (holds return address)

pc
     program counter

mach
macl
     high and low multiply accumulator registers

sr
     status register

gbr
     global base register

vbr
     vector base register (for interrupt vectors)

Addressing Modes
----------------

AS understands the following addressing modes for the SH. RN in the following refers to any of the numbered registers, but not the control registers.

RN
     Register direct

@RN
     Register indirect

@-RN
     Register indirect with pre-decrement

@RN+
     Register indirect with post-increment

@(DISP, RN)
     Register indirect with displacement

@(R0, RN)
     Register indexed

@(DISP, GBR)
     GBR offset

@(R0, GBR)
     GBR indexed

ADDR
@(DISP, PC)
     PC relative address (for branch or for addressing memory).  The AS implementation allows you to use the simpler form ADDR anywhere a PC relative address is called for; the alternate form is supported for compatibility with other assemblers.

#IMM
     Immediate data

Floating Point
==============

SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other SH groups can use .float directive to generate IEEE floating-point numbers.

SH2E and SH3E support single-precision floating point calculations as well as entirely PCAPI compatible emulation of double-precision floating point calculations. SH2E and SH3E instructions are a subset of the floating point calculations conforming to the IEEE754 standard.

In addition to single-precision and double-precision floating-point operation capability, the on-chip FPU of SH4 has a 128-bit graphic engine that enables 32-bit floating-point data to be processed 128 bits at a time. It also supports 4 * 4 array operations and inner product operations. Also, a superscalar architecture is employed that enables simultaneous execution of two instructions (including FPU instructions), providing performance of up to twice that of conventional architectures at the same frequency.

SH Machine Directives
=====================

uaword
ualong
     AS will issue a warning when a misaligned .word or .long directive is used.  You may use .uaword or .ualong to indicate that the value is intentionally misaligned.

Opcodes
=======

For detailed information on the SH machine instruction set, see SH-Microcomputer User's Manual (Renesas) or SH-4 32-bit CPU Core Architecture (SuperH) and SuperH (SH) 64-Bit RISC Series (SuperH).

AS implements all the standard SH opcodes.  No additional pseudo-instructions are needed on this family.  Note, however, that because AS supports a simpler form of PC-relative addressing, you may simply write (for example)

     mov.l  bar,r0

where other assemblers might require an explicit displacement to bar from the program counter:

     mov.l  @(DISP, PC)