Subversion Repositories openmsp430

2012-05-30 [r145]  

        * Add Dhrystone and CoreMark benchmarks to the simulation
          environment.

2012-05-09 [r142]  

        * Beautify the linker script examples.

2012-05-05 [r141]  

        * Update verification environment to support MSPGCC Uniarch (based
          on GCC 4.5 and later)

2012-04-23 [r139]  

        * Add some SVN ignore patterns

2012-04-23 [r138]  

        * Update simulation scripts to support Cygwin out of the box for
          Windows users.

2012-03-22 [r134]  

        * Add full ASIC support (low-power modes, DFT, ...). Improved
          serial debug interface reliability.

2012-03-09 [r132]  

        * Update FPGA examples with the POP.B bug fix

2012-03-01 [r130]  

        * Fixed POP.B bug (see Bugtracker
          http://opencores.org/bug,assign,2137 )

2011-12-16 [r128]  

        * Fixed CALL x(SR) bug (see Bugtracker
          http://opencores.org/bug,view,2111 )

2011-10-05 [r122]  

        * Add coverage report generation (NCVERILOG only) Add support for
          the ISIM Xilinx simulator.

2011-06-23 [r117]  

        * To facilitate commercial adoption of the openMSP430, the core has
          moved to a modified BSD license.

2011-05-29 [r115]  

        * Add linker script example.

2011-05-21 [r112]  

        * Modified comment.

2011-05-20 [r111]  

        * Re-organized the "openMSP430_defines.v" file. Re-defined the
          CPU_ID register of the debug interface (in particular to support
          custom user versioning). Added RTL configuration possibility to
          expand the peripheral address space from 512B (0x0000 to 0x0200)
          to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr
          bus width goes from 8 to 14 bits and the peripherals address
          decoders have been updated accordingly.

2011-03-25 [r106]  

        * Separated the Timer A defines from the openMSP430 ones. Added the
          "dbg_en" port in order to allow a separate reset of the debug
          interface. Added the "core_en" port (when cleared, the CPU will
          stop execution, the dbg_freeze signal will be set and the aclk &
          smclk will be stopped). Renamed "per_wen" to "per_we" to prevent
          confusion with active low signals. Removed to missing unused
          flops when the DBG_EN is not defined (thanks to Mihai
          contribution).

2011-03-10 [r105]  

        * Removed dummy memory read access for the MOV/PUSH/CALL/RETI
          instructions. These were not problematic but this is simply
          cleaner that way.

2011-03-05 [r103]  

        * Removed the timescale from all RTL files. Added possibility to
          exclude the "includes" statements from the RTL.

2011-03-04 [r102]  

        * Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955
          ). The following PUSH instructions are now working as expected: -
          indexed mode: PUSH x(R1) - indirect register mode: PUSH @R1 -
          indirect autoincrement: PUSH @R1+

2011-03-04 [r101]  

        * Cosmetic change in order to prevent an X propagation whenever
          executing a byte instruction with an uninitialized memory
          location as source.

2011-02-28 [r99]  

        * Small fix for CVER simulator support.

2011-02-28 [r98]  

        * Added support for VCS verilog simulator. VPD and TRN waveforms
          can now be generated.

2011-02-24 [r95]  

        * Update some test patterns for the additional simulator supports.

2011-02-24 [r94]  

        * Thanks to Mihai-Costin Manolescu's contribution, the simulation
          scripts now support the following simulators: - Icarus Verilog -
          Cver - Verilog-XL - NCVerilog - Modelsim

2011-02-20 [r91]  

        * Fixed bug when an IRQ arrives while CPU is halted through the
          serial debug interface. This bug is CRITICAL for people using
          working with interrupts and the Serial Debug Interface.

2011-01-28 [r86]  

        * Update serial debug interface test patterns to make them work
          with all program memory configurations.

2011-01-28 [r85]  

        * Diverse RTL cosmetic updates.

2011-01-23 [r84]  

        * Update SRAM model in the core testbench to prevent the IEEE
          warning when running simulations. Update watchdog to fix NMI
          synchronisation problem. Add synchronizers for the PUC signal in
          the debug interface.

2010-12-05 [r80]  

        * Create initial version of the Actel FPGA implementation example.

2010-11-23 [r79]  

        * Update the GPIO peripheral to fix a potential synchronization
          issue.

2010-11-18 [r76]  

        * Add possibility to simulate C code within the "core" environment.

2010-08-28 [r74]  

        * Update serial debug interface to support memories with a size
          which is not a power of 2. Update the software tools accordingly.

2010-08-03 [r73]  

        * Update all bash scripts headers with "#!/bin/bash" instead of
          "#!/bin/sh". This will prevent compatibility problems in systems
          where bash isn't the default shell.

2010-08-01 [r72]  

        * Expand configurability options of the program and data memory
          sizes.

2010-03-07 [r67-68]  

        * Update synthesis scripts with the hardware multiplier support.

        * Added 16x16 Hardware Multiplier.

2010-03-07 [r66]  

        * The peripheral templates are now under BSD license. Developers of
          new peripherals based on these templates won't have to disclose
          their code.

2010-02-24 [r65]  

        * Add possibility to disable waveform dumping by setting the
          OMSP_NODUMP environment variable to 1.

2010-02-14 [r64]  

        * Add Actel synthesis environment for size and speed analysis.

2010-02-14 [r63]  

        * Add Altera synthesis environment for size and speed analysis.

2010-02-14 [r62]  

        * Add Xilinx synthesis environment for size&speed analysis.

2010-02-03 [r60]  

        * Cleanup of the PC (R0) generation logic. Formal equivalence was
          shown between the new and old code with Synopsys' Formality (to
          make sure that nothing has been broken :-P ).

2010-02-01 [r58]  

        * Update the debug hardware breakpoint verification patterns to
          reflect the latest design updates.

2010-02-01 [r57]  

        * Update design to exclude the range mode from the debug hardware
          breakpoint units. As this feature is not used by GDB, it has been
          disabled in order to improve the timings and save a bit of
          area/utilisation. Note that if required, this feature can be
          re-enabled through the `HWBRK_RANGE define located in the
          "openMSP430_defines.v" file.

2010-01-28 [r56]  

        * Update Design Compiler Synthesis scripts.

2010-01-27 [r55]  

        * Add a "sandbox" test pattern to play around with the simulation
          :-P

2010-01-27 [r54]  

        * Update FPGA projects with the combinatorial loop fixed.

2010-01-27 [r53]  

        * Fixed the following combinatorial timing loop: 1- irq_detect
          (omsp_frontend) 2- decode (omsp_frontend) 3- dbg_swbrk (omsp_dbg)
          4- halt_flag_set (omsp_dbg) 6- dbg_halt_cmd (omsp_dbg) 7-
          irq_detect (omsp_frontend) Without this fix, problem could occur
          whenever an IRQ request arrives during a software breakpoint
          instruction fetch.

2009-12-29 [r34]  

        * To avoid potential conflicts with other Verilog modules in bigger
          projects, the openMSP430 sub-modules have all been renamed with
          the "omsp_" prefix.

2009-12-29 [r33]  

        * In order to avoid confusion, the following changes have been
          implemented to the Verilog code: - renamed the "rom_*" ports and
          defines to "pmem_*" (program memory). - renamed the "ram_*" ports
          and defines to "dmem_*" (data memory). In addition, in order to
          prevent potential conflicts with the Verilog defines of other
          IPs, a Verilog undefine file has been created.

2009-08-30 [r23]  

        * Renamed the "openMSP430.inc" file to "openMSP430_defines.v" &
          added the "timescale.v" file. In order to follow the same
          structure as other OpenCores projects, the timescale and the
          defines are now included from within the Verilog files (using the
          `include construct).

2009-08-04 [r19]  

        * added SVN property for keywords

2009-08-04 [r18]  

        * Updated headers with SVN info

2009-08-04 [r17]  

        * Updated header with SVN info

2009-07-13 [r6]  

        * Some more SVN ignore properties...

2009-06-30 [r2]  

        * Upload complete openMSP430 project to the SVN repository