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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 SINGLE-OPERAND ARITHMETIC: SXT  INSTRUCTION               */
/*---------------------------------------------------------------------------*/
/* Test the SXT  instruction.                                                */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
/*===========================================================================*/

.set    DMEM_BASE, (__data_start     )
.set    DMEM_200,  (__data_start+0x00)
.set    DMEM_202,  (__data_start+0x02)
.set    DMEM_204,  (__data_start+0x04)
.set    DMEM_206,  (__data_start+0x06)
.set    DMEM_208,  (__data_start+0x08)
.set    DMEM_209,  (__data_start+0x09)
.set    DMEM_20A,  (__data_start+0x0A)
.set    DMEM_20B,  (__data_start+0x0B)
.set    DMEM_20C,  (__data_start+0x0C)
.set    DMEM_20D,  (__data_start+0x0D)
.set    DMEM_20E,  (__data_start+0x0E)
.set    DMEM_20F,  (__data_start+0x0F)
.set    DMEM_210,  (__data_start+0x10)
.set    DMEM_212,  (__data_start+0x12)
.set    DMEM_214,  (__data_start+0x14)
.set    DMEM_216,  (__data_start+0x16)
.set    DMEM_218,  (__data_start+0x18)
.set    DMEM_219,  (__data_start+0x19)
.set    DMEM_21A,  (__data_start+0x1A)
.set    DMEM_21B,  (__data_start+0x1B)
.set    DMEM_21C,  (__data_start+0x1C)
.set    DMEM_21D,  (__data_start+0x1D)
.set    DMEM_21E,  (__data_start+0x1E)
.set    DMEM_21F,  (__data_start+0x1F)
.set    DMEM_220,  (__data_start+0x20)
.set    DMEM_222,  (__data_start+0x22)
.set    DMEM_224,  (__data_start+0x24)

.global main

main:
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */


        # Addressing mode: Rn
        #------------------------

        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, r4
        sxt          r4            ;# SXT (r4=0x7524  =>  r4=0x0024)
        mov          r2, r5

        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, r6
        sxt          r6            ;# SXT (r6=0x1cb6  =>  r6=0xffb6)
        mov          r2, r7

        mov     #0x1000, r15


        # Addressing mode: @Rn
        #------------------------

        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_200
        mov   #DMEM_200, r4
        mov     #0xaaaa, &DMEM_202
        sxt         @r4            ;# SXT (mem00=0x7524  => {mem00=0x0024)
        mov          r2, r5

        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_202
        mov   #DMEM_202, r6
        mov     #0xaaaa, &DMEM_204
        sxt         @r6            ;# SXT (mem01=0x1cb6  => {mem01=0xffb6)
        mov          r2, r7

        mov     #0x2000, r15


        # Addressing mode: @Rn+
        #------------------------

        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_208
        mov   #DMEM_208, r4
        mov     #0xaaaa, &DMEM_20A
        sxt        @r4+            ;# SXT (mem04=0x7524  => {mem04=0x0024)
        mov          r2, r5

        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_20A
        mov   #DMEM_20A, r6
        mov     #0xaaaa, &DMEM_20C
        sxt        @r6+            ;# SXT (mem05=0x1cb6  => {mem05=0xffb6)
        mov          r2, r7

        mov     #0x3000, r15


        # Addressing mode: X(Rn)
        #------------------------

        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_210
        mov   #DMEM_200, r4
        mov     #0xaaaa, &DMEM_212
        sxt       16(r4)            ;# SXT (mem08=0x7524  => {mem08=0x0024)
        mov          r2, r5

        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_212
        mov   #DMEM_200, r6
        mov     #0xaaaa, &DMEM_214
        sxt       18(r6)            ;# SXT (mem09=0x1cb6  => {mem09=0xffb6)
        mov          r2, r7

        mov     #0x4000, r15


        # Addressing mode: EDE
        #------------------------
.set   EDE_218,  DMEM_218
.set   EDE_21A,  DMEM_21A
.set   EDE_21C,  DMEM_21C
.set   EDE_21E,  DMEM_21E

        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_218
        mov     #0xaaaa, &DMEM_21A
        sxt     EDE_218            ;# SXT (mem0c=0x7524  => {mem0c=0x0024)
        mov          r2, r5

        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_21A
        mov     #0xaaaa, &DMEM_21C
        sxt     EDE_21A            ;# SXT (mem0d=0x1cb6  => {mem0d=0xffb6)
        mov          r2, r7

        mov     #0x5000, r15


        # Addressing mode: &EDE
        #------------------------
.set   aEDE_220,  DMEM_220
.set   aEDE_222,  DMEM_222
.set   aEDE_224,  DMEM_224
.set   aEDE_226,  DMEM_226

        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_220
        mov     #0xaaaa, &DMEM_222
        sxt   &aEDE_220            ;# SXT (mem10=0x7524  => {mem10=0x0024)
        mov          r2, r5

        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_222
        mov     #0xaaaa, &DMEM_224
        sxt   &aEDE_222            ;# SXT (mem11=0x1cb6  => {mem11=0xffb6)
        mov          r2, r7

        mov     #0x6000, r15


        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff


        /* ----------------------         INTERRUPT VECTORS  --------------- */

.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    <unused>
.word end_of_test  ; Interrupt  1                      <unused>
.word end_of_test  ; Interrupt  2                      <unused>
.word end_of_test  ; Interrupt  3                      <unused>
.word end_of_test  ; Interrupt  4                      <unused>
.word end_of_test  ; Interrupt  5                      <unused>
.word end_of_test  ; Interrupt  6                      <unused>
.word end_of_test  ; Interrupt  7                      <unused>
.word end_of_test  ; Interrupt  8                      <unused>
.word end_of_test  ; Interrupt  9                      <unused>
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      <unused>
.word end_of_test  ; Interrupt 12                      <unused>
.word end_of_test  ; Interrupt 13                      <unused>
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET