Subversion Repositories openmsp430

//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: openMSP430_fpga.prj
// 
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 37 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-12-29 21:58:14 +0100 (Tue, 29 Dec 2009) $
//----------------------------------------------------------------------------

//=============================================================================
// FPGA Specific modules
//=============================================================================
`include "../src/arch.v"
`include "../src/openMSP430_fpga.v"

`ifdef SPARTAN3
   `include "../src/coregen/spartan3_pmem.v"
   `include "../src/coregen/spartan3_dmem.v"
`endif
`ifdef SPARTAN3E
   `include "../src/coregen/spartan3e_pmem.v"
   `include "../src/coregen/spartan3e_dmem.v"
`endif
`ifdef SPARTAN3A
   `include "../src/coregen/spartan3a_pmem.v"
   `include "../src/coregen/spartan3a_dmem.v"
`endif
`ifdef SPARTAN3ADSP
   `include "../src/coregen/spartan3adsp_pmem.v"
   `include "../src/coregen/spartan3adsp_dmem.v"
`endif
`ifdef SPARTAN6
   `include "../src/coregen/spartan6_pmem.v"
   `include "../src/coregen/spartan6_dmem.v"
`endif
`ifdef VIRTEX4
   `include "../src/coregen/virtex4_pmem.v"
   `include "../src/coregen/virtex4_dmem.v"
`endif
`ifdef VIRTEX5
   `include "../src/coregen/virtex5_pmem.v"
   `include "../src/coregen/virtex5_dmem.v"
`endif
`ifdef VIRTEX6
   `include "../src/coregen/virtex6_pmem.v"
   `include "../src/coregen/virtex6_dmem.v"
`endif


//=============================================================================
// openMSP430
//=============================================================================

`include "../../../rtl/verilog/openMSP430.v"
`include "../../../rtl/verilog/omsp_frontend.v"
`include "../../../rtl/verilog/omsp_execution_unit.v"
`include "../../../rtl/verilog/omsp_register_file.v"
`include "../../../rtl/verilog/omsp_alu.v"
`include "../../../rtl/verilog/omsp_sfr.v"
`include "../../../rtl/verilog/omsp_clock_module.v"
`include "../../../rtl/verilog/omsp_mem_backbone.v"
`include "../../../rtl/verilog/omsp_watchdog.v"
`include "../../../rtl/verilog/omsp_sync_cell.v"
`include "../../../rtl/verilog/omsp_sync_reset.v"

`include "../src/openMSP430_defines.v"
`ifdef DBG_EN
   `include "../../../rtl/verilog/omsp_dbg.v"
   `include "../../../rtl/verilog/omsp_dbg_uart.v"
   `include "../src/openMSP430_defines.v"
   `ifdef DBG_HWBRK_0
      `include "../../../rtl/verilog/omsp_dbg_hwbrk.v"
   `endif
`endif
`include "../src/openMSP430_defines.v"
`ifdef MULTIPLIER
   `include "../../../rtl/verilog/omsp_multiplier.v"
`endif