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openMSP430
Basic Clock Module (ASIC)
LFXT_CLK
DCO_CLK
Low Frequency
clock source
(LFXT)
ACLK
SMCLK
DCO_ENABLE
DCO_WKUP
High Frequency
clock source
(DCO)
LFXT_ENABLE
LFXT_WKUP
WKUP
MCLK
LFXT_DOMAIN
ACLK_DIVIDER
DCO_CLK
MCLK_MUX
SMCLK_MUX
MCLK_DIVIDER
SMCLK_DIVIDER
CPUOFF_EN
SCG1_EN
OSCOFF_EN
DIVAx
DIVMx
Divider
1/2/4/8
Divider
1/2/4/8
DIVSx
Divider
1/2/4/8
SELS
1
0
1
0
SCG1
CPUOFF
OSCOFF
SCG0
SCG0_EN
Glitch free logic
Glitch free logic
SELMx[1]