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0x4 (MEM_CTL)
Data
Host TX:
Host RX:
Command frame
Data frame
1
0
mem
reg
B/W
0
Burst Frames
x MEM_CNT x (2-MEM_CTL.B/W)
NACK
Stop
ACK
ACK
oMSP core Address
Start
ACK
SCL
SDA
MSB
LSB
WR
Cmd Frame (write to MEM_CTL)
LSB
MSB
ACK
I2C
A6
A5
A4
A3
A2
A1
A0
Write Data (to MEM_CTL)
LSB
MSB
ACK
1
1
B/W
MEM/
REG
0
0
0
1
0
0
0
1
Read Data Burst
LSB
MSB
ACK
MEM_CNT * (2 – MEM_CTL.B/W )
oMSP core Address
Rep.
Start
MSB
LSB
A6
A5
A4
A3
A2
A1
A0
RD
ACK