page3
MCLK
DMA_ADDR[15:1]
Control
DMA_DIN[15:0]
DMA_READY
DMA_DOUT[15:0]
Multiple transfers
A
Control
(A)
Data
(A)
Data
(A)
B
Data
(B)
Data
(B)
Data
(C)
Control
(B)
C
Data
(C)
Control
(C)