page4
MCLK
DMA_ADDR[15:1]
Control
DMA_DIN[15:0]
DMA_READY
DMA_DOUT[15:0]
A
Control
(A)
Data
(A)
Error response
DMA_RESP
B
Control
(B)
Data
(B)
Data
(B)
Invalid Data
(A)