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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [coregen.cgc] - Rev 171
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<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>Verilog</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
<xilinx:packageInfo>
<xilinx:sourceCoreCreationDate>2012-06-25+21:54</xilinx:sourceCoreCreationDate>
</xilinx:packageInfo>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc6slx9</xilinx:device>
<xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
<xilinx:package>csg324</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
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<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
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<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:design>
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