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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [rtl/] [verilog/] [coregen/] [ram_16x1k_dp.asy] - Rev 222

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Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 ram_16x1k_dp
RECTANGLE Normal 32 32 544 1376
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[9:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName dina[15:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName ena
PINATTR Polarity IN
LINE Wide 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wea[1:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[9:0]
PINATTR Polarity IN
LINE Wide 0 464 32 464
PIN 0 464 LEFT 36
PINATTR PinName dinb[15:0]
PINATTR Polarity IN
LINE Normal 0 496 32 496
PIN 0 496 LEFT 36
PINATTR PinName enb
PINATTR Polarity IN
LINE Wide 0 560 32 560
PIN 0 560 LEFT 36
PINATTR PinName web[1:0]
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName douta[15:0]
PINATTR Polarity OUT
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[15:0]
PINATTR Polarity OUT

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