URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [coregen/] [coregen.log] - Rev 2
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Welcome to Xilinx CORE Generator.Opened project file/home/pitchu/Projects/verilog/openMSP430/fpga/diligent_s3board/rtl/verilog/coregen/coregen.cgp.Customizing IP...WARNING! Program tries to unlock a connection without having acquireda lock first, which indicates a programming error.There will be no further warnings about this issue.libxcb: WARNING! Program tries to lock an already locked connection,which indicates a programming error.There will be no further warnings about this issue.Finished Customizing.Generating IP...WARNING! Program tries to unlock a connection without having acquireda lock first, which indicates a programming error.There will be no further warnings about this issue.libxcb: WARNING! Program tries to lock an already locked connection,which indicates a programming error.There will be no further warnings about this issue.Generating Implementation files.Generating ISE symbol file...Generating NGC file.Finished Generating.Successfully generated rom_8x2k_hi.Customizing IP...Finished Customizing.Generating IP...WARNING! Program tries to unlock a connection without having acquireda lock first, which indicates a programming error.There will be no further warnings about this issue.libxcb: WARNING! Program tries to lock an already locked connection,which indicates a programming error.There will be no further warnings about this issue.Generating Implementation files.Generating ISE symbol file...Generating NGC file.Finished Generating.Successfully generated rom_8x2k_lo.Closed project file.
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