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OpenRISC 1200 version 2

Supplementary Programmer's Reference Manual

Jeremy Bennett

Revision 0.0.3

9 Jun 2010

Revision History

When updating this revision history, ensure the bookmark revno is updated to reside on the latest revision number and revdate to reside on the revision date.

Revision	Date	Author	Description
0.0.1	27 Apr 2010	Jeremy Bennett	Initial draft, covering just PIC
0.0.2	2 Jun 2010	Jeremy Bennett	Documentation around lf.madd.s and FPU SPRs clarified
0.0.3	9 Jun 2010	Jeremy Bennett	Range exceptions clarified for l.add, l.addc, l.addi and l.addic instructions. Exception behavior of l.div and l.divu instructions clarified.

Table of Contents

1	About this Manual	8

1.1	Introduction	8

1.2	Authors and Contributors	8

1.3	Typography	8

1.4	Conventions	9

1.5	Numbering	9

2	Architecture Overview	10

3	Addressing Modes and Operand Conventions	11

4	Register Set	12

4.1	Features	12

4.2	Overview	12

4.3	Special Purpose Registers	12

4.4	General Purpose Registers	12

4.5	Support for Custom Number of GPRs	12

4.6	Supervision Register	12

4.7	Exception Program Counter Registers	12

4.8	Exception Effective Address Registers	12

4.9	Exception Supervision Registers	12

4.10	Next and Previous Program Counter	12

4.11	Floating Point Control Status Register	12

5	Instruction Set	13

5.1	Features	13

5.2	Overview	13

5.3	ORBIS32/64	13

5.4	ORFPX32/64	18

5.5	ORVDX64	21

6	Exception Model	22

7	Memory Model	23

8	Memory Management	24

9	Cache Model and Cache Coherency	25

10	Debug Unit (Optional)	26

11	Performance Counters Unit (Optional)	27

12	Power Management (Optional)	28

13	Programmable Interrupt Controller (Optional)	29

13.1	Functionality	29

14	Tick Timer Facility (Optional)	31

15	OpenRISC 1000 Implementations	32

16	Application Binary Interface	33

Acronyms & Abbreviations

ETLA	Extended TLA
PIC	Programmable Interrupt Controller
PICMR	PIC Mask Register
PICSR	PIC Status Register
TLA	Three Letter Acryonym
UPR	Unit Present Register

Table 1‑1. Acronyms and Abbreviations

References

Damjan Lampret, 6 Sep 01. OpenRISC 1200 IP Core Specification, rev 0.7. Available from www.opencores.org.

Igor Mohor, 14 Apr 04. SoC Debug Interface, rev 3.0. Available from www.opencores.org.

OpenCores, 25 Nov 05. OpenRISC 1000 Architecture Manual. Available from www.opencores.org.

About this Manual

Introduction

The OpenRISC 1000 system architecture manual [3] defines the architecture for a family of open-source, synthesizable RISC microprocessor cores. The OpenRISC 1200 is a 32-bit implementation of that architecture [1].

A new version of the OpenRISC 1200 was created by engineers from ORSoC AB in 2009 and published at www.opencores.org. This new version makes a number of improvements to the original implementation.

As the basis for design, the architecture and specification documents are fixed. This document exists to capture information about changes from those specifications and to give further detail and clarification where required.

This document is currently an OpenOffice document controlled under Subversion at www.opencores.org. Its dynamic nature means that it would be better represented in a Wiki, when that becomes available.

The chapters of the document match those in the architecture manual for convenience [3]. However this does mean that early revisions have a large number of empty chapters.

Authors and Contributors

The main authors are shown on the title page. However the contents of this document draw on the contributions of the wider OpenRISC community, who we list here in alphabetical order.

If you have contributed to this manual but your name isn't listed here, it is not meant as a slight―we simply don't know about it. Send an email to the author of the latest revision, and we'll correct the situation.

Name	Contribution
Julius Baxter	Advice on PIC operation
John Eaton	Advice on PIC operation
Raul Fajardo	Advice on PIC operation

Table 1‑2. Contributors to this manual.

Typography

In this manual, fonts are used as follows:

Programming examples are shown in a fixed width font, thus.

Emphasis is shown thus, strong emphasis, thus.

UPPER CASE items may be either acronyms or register mode fields that can be written by software. Some common acronyms appear in the glossary.

Square brackets [] indicate an addressed field in a register or a numbered register in a register file.

However users should take advantage of the OpenOffice styles which have been created to enforce this.

Conventions

l.mnemonic	Identifies an ORBIS32/64 instruction.
lv.mnemonic	Identifies an ORVDX32/64 instruction.
lf.mnemonic	Identifies an ORFPX32/64 instruction.
0x	Indicates a hexadecimal number.
rA	Instruction syntax used to identify a general purpose register
REG[FIELD]	Syntax used to identify specific bit(s) of a general or special purpose register. FIELD can be a name of one bit or a group of bits or a numerical range constructed from two values separated by a colon.
X	In certain contexts, this indicates a ‘don't care’.
N	In certain contexts, this indicates an undefined numerical value.
Implementation	An actual processor implementing the OpenRISC 1000 architecture.
Unit	Sometimes referred to as a coprocessor. An implemented unit usually with some special registers and controlling instructions. It can be defined by the architecture or it may be custom.
Exception	A vectored transfer of control to supervisor software through an exception vector table. A way in which a processor can request operating system assistance (division by zero, TLB miss, external interrupt etc).
Privileged	An instruction (or register) that can only be executed (or accessed) when the processor is in supervisor mode (when SR[SM]=1).

Table 1‑3. Conventions

Numbering

All numbers are decimal or hexadecimal unless otherwise indicated. The prefix 0x indicates a hexadecimal number. Decimal numbers don't have a special prefix. Binary and other numbers are marked with their base.

Architecture Overview

Addressing Modes and Operand Conventions

Register Set

Features

Overview

Special Purpose Registers

Group 11 is shown as being reserved for the Floating Point Unit, although no registers are described (the floating point control status register, FPCSR, is in Group 0).

The floating point opcodes, lf.madd.d and lf.madd.s, in the original architecture manual refer to two floating point SPRs, FPMADDLO and FPMADDHI. However this appears to be an anomaly. This manual documents revised specifications, which are purely register based. See Section 5.4 for details.

General Purpose Registers

Support for Custom Number of GPRs

Supervision Register

Exception Program Counter Registers

Exception Effective Address Registers

Exception Supervision Registers

Next and Previous Program Counter

Floating Point Control Status Register

Instruction Set

Features

Overview

ORBIS32/64

l.add	Add Signed	l.add

31	.	.	.	.	26	25	.	.	.	21	20	.	.	.	16	15	.	.	.	11	10	9	8	7	.	.	4	3	.	.	0
opcode 0x38	D	A	B	res	0x0	reserved	opcode 0x0
6 bits	5 bits	5 bits	5 bits	1	2 bits	4 bits	4 bits

Format:

l.add rD,rA,rB

Description

The contents of general purpose register rA are added to the contents of general purpose register rB to form the result. The result is placed into general purpose register rD.

32-bit Implementation

rD[31:0] ← rA[31:0] + rB[31:0]

SR[CY] ← carry

SR[OV] ← overflow

64-bit Implementation

rD[63:0] ← rA[63:0] + rB[63:0]

SR[CY] ← carry

SR[OV] ← overflow

Exceptions

Range Exception on overflow if SR[OVE] is set.

Note. This is a clarification of the original manual.

l.addc	Add Signed and Carry	l.addc

31	.	.	.	.	26	25	.	.	.	21	20	.	.	.	16	15	.	.	.	11	10	.	8	7	.	.	.	.	.	.	0
opcode 0x38	D	A	B	res	0x0	reserved	opcode 0x1
6 bits	5 bits	5 bits	5 bits	1	2 bits	4 bits	4 bits

Format:

l.addc rD,rA,rB

Description

The contents of general purpose register rA are added to the contents of general purpose register rB and carry, SR[CY], to form the result. The result is placed into general purpose register rD.

32-bit Implementation

rD[31:0] ← rA[31:0] + rB[31:0] + SR[CY]

SR[CY] ← carry

SR[OV] ← overflow

64-bit Implementation

rD[63:0] ← rA[63:0] + rB[63:0] + SR[CY]

SR[CY] ← carry

SR[OV] ← overflow

Exceptions

Range Exception on overflow if SR[OVE] is set.

Note. This is a clarification of the original manual.

l.addi	Add Immediate Signed	l.addi

31	.	.	.	.	26	25	.	.	.	21	20	.	.	.	16	15	.	.	.	11	10	.	8	7	.	.	.	.	.	.	0
opcode 0x27	D	A	I
6 bits	5 bits	5 bits	16 bits

Format:

l.addi rD,rA,I

Description

The immediate value is sign extended and added to the contents of general purpose register rA to form the result. The result is placed into general purpose register rD.

32-bit Implementation

rD[31:0] ← rA[31:0] + exts(Immediate)

SR[CY] ← carry

SR[OV] ← overflow

64-bit Implementation

rD[63:0] ← rA[63:0] + exts(Immediate)

SR[CY] ← carry

SR[OV] ← overflow

Exceptions

Range Exception on overflow if SR[OVE] is set.

Note. This is a clarification of the original manual.

l.addic	Add Immediate Signed and Carry	l.addic

31	.	.	.	.	26	25	.	.	.	21	20	.	.	.	16	15	.	.	.	11	10	.	8	7	.	.	.	.	.	.	0
opcode 0x28	D	A	I
6 bits	5 bits	5 bits	16 bits

Format:

l.addic rD,rA,I

Description

The immediate value is sign extended and added to the contents of general purpose register rA and carry, SR[CY], to form the result. The result is placed into general purpose register rD.

32-bit Implementation

rD[31:0] ← rA[31:0] + exts(Immediate) + SR[CY]

SR[CY] ← carry

SR[OV] ← overflow

64-bit Implementation

rD[63:0] ← rA[63:0] + exts(Immediate) + SR[CY]

SR[CY] ← carry

SR[OV] ← overflow

Exceptions

Range Exception on overflow if SR[OVE] is set.

Note. This is a clarification of the original manual.

l.div	Divide Signed	l.div

31	.	.	.	.	26	25	.	.	.	21	20	.	.	.	16	15	.	.	.	11	10	.	8	7	.	.	.	.	.	.	0
opcode 0x38	D	A	B	res	0x3	reserved	opcode 0x9
6 bits	5 bits	5 bits	5 bits	1	2 bits	4 bits	4 bits

Format:

l.div rD,rA,rB

Description

The contents of general purpose register rA are divided by the contents of general purpose register rB, to form the result. Both operands are treated as signed integers. The result is placed into general purpose register rD. The carry flag, SR[CY] is set when the divisor is zero.

Note. Change from original manual. Correct values shown for carry and overflow.

32-bit Implementation

rD[31:0] ← rA[31:0] / rB[31:0]

SR[CY] ← rB[31:0] == 0

SR[OV] ← 0

64-bit Implementation

rD[63:0] ← rA[63:0] / rB[63:0]

SR[CY] ← rB[63:0] == 0

SR[OV] ← 0

Exceptions

Range exception when divisor is zero.

l.divu	Divide Unsigned	l.divu

31	.	.	.	.	26	25	.	.	.	21	20	.	.	.	16	15	.	.	.	11	10	.	8	7	.	.	.	.	.	.	0
opcode 0x38	D	A	B	res	0x3	reserved	opcode 0xa
6 bits	5 bits	5 bits	5 bits	1	2 bits	4 bits	4 bits

Format:

l.div rD,rA,rB

Description

The contents of general purpose register rA are divided by the contents of general purpose register rB, to form the result. Both operands are treated as unsigned integers. The result is placed into general purpose register rD. The carry flag, SR[CY] is set when the divisor is zero.

Note. Change from original manual. Correct values shown for carry and overflow.

32-bit Implementation

rD[31:0] ← rA[31:0] / rB[31:0]

SR[CY] ← rB[31:0] == 0

SR[OV] ← 0

64-bit Implementation

rD[63:0] ← rA[63:0] / rB[63:0]

SR[CY] ← rB[63:0] == 0

SR[OV] ← 0

Exceptions

Range exception when divisor is zero.

ORFPX32/64

This section is not separated from ORBIS32/64 in the original manual.

This manual documents changed instructions only.

lf.madd.d	Multiply and Add Floating Point Double Precision	lf.madd.d

31	.	.	.	.	26	25	.	.	.	21	20	.	.	.	16	15	.	.	.	11	10	.	8	7	.	.	.	.	.	.	0
opcode 0x32	D	A	B	reserved	opcode 0x17
6 bits	5 bits	5 bits	5 bits	3 bits	8 bits

Format:

lf.madd.d rD,rA,rB

Description

The contents of general purpose register rA are multipled by the contents of general purpose register rB, and added to the general purpose register rD.

32-bit Implementation

N/A

64-bit Implementation

rD[63:0] ← rA[63:0] * rB[63:0] + rD[63:0]

Exceptions

Floating Point

lf.madd.s	Multiply and Add Floating Point Single Precision	lf.madd.s

31	.	.	.	.	26	25	.	.	.	21	20	.	.	.	16	15	.	.	.	11	10	.	8	7	.	.	.	.	.	.	0
opcode 0x32	D	A	B	reserved	opcode 0x7
6 bits	5 bits	5 bits	5 bits	3 bits	8 bits

Format:

lf.madd.s rD,rA,rB

Description

The contents of general purpose register rA are multipled by the contents of general purpose register rB, and added to the general purpose register rD.

32-bit Implementation

rD[31:0] ← rA[31:0] * rB[31:0] + rD[31:0]

64-bit Implementation

rD[31:0] ← rA[31:0] * rB[31:0] + rD[31:0]

rD[63:32] ← 0

Exceptions

Floating Point

ORVDX64

This section is not separated from ORBIS32/64 in the original manual.

Exception Model

Memory Model

Memory Management

Cache Model and Cache Coherency

Debug Unit (Optional)

The debug interface from a programmer's perspective is unchanged in the OpenRISC 1200 version 2. However a new physical debug interface has been adopted [2]. This will affect those concerned with the representation of JTAG packets to drive the debug interface.

Performance Counters Unit (Optional)

Power Management (Optional)

Programmable Interrupt Controller (Optional)

The OpenRISC 1000 Architecture Manual [] describes an optional simple programmer interrupt controller (PIC) capable of handling up to 32 separate interrupt lines driving the Interrupt Exception. The presence of the PIC is indicated in the Unit Present Register bby UPR[PICP].

The PIC is controlled by two registers, PICMR and PICSR. PICMR is a mask for the incoming interrupts. PICSR is a status register indicating which interrupt lines have been asserted. By convention, interrupts 0 and 1 in PICMR are tied to 1, so that these interrupts lines are non-maskable.

A simple block diagram of the PIC is shown in Figure 13-1.

Mask function PICSR INT[31:0] External interrupt exception PICMR Figure 13-1: Testing

Functionality

In the OpenRISC 1200 version 2, the functionality has changed. The PIC offers a latched level-sensitive interrupt.

Once an interrupt line is latched (i.e. its value appears in PICSR), no new interrupts can be triggered for that line until its bit in PICSR is cleared. The usual sequence for an interrupt handler is then as follows.

Peripheral asserts interrupt, which is latched and triggers handler.

Handler processes interrupt.

Handler notifies peripheral that the interrupt has been processed (typically via a memory mapped register).

Peripheral deasserts interrupt.

Handler clears corresponding bit in PICSR and returns.

It is assumed that the peripheral will deassert its interrupt promptly (within 1-2 cycles). Otherwise on exiting the interrupt handler, having cleared PICSR, the level sensitive interrupt will immediately retrigger.

Tick Timer Facility (Optional)

OpenRISC 1000 Implementations

Application Binary Interface

There have been some minor changes in the ABI used with the OpenRISC 1200 version 2.