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https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
[/] [openrisc/] [trunk/] [or1k_startup/] [backend/] [ACTEL/] [smartgen/] [flash/] [flash.log] - Rev 728
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** Message System Log
** Database:
** Date: Mon Mar 16 11:22:43 2009
****************
Macro Parameters
****************
Name : flash
Family : ProASIC3
Output Format : VERILOG
Type : UFROM
MEMFILE : flash.mem
ACT_PROGFILE : flash.ufc
**************
Compile Report
**************
Warning: For versions of the A3P1000 device that do not have a 'C' after the
device packing datecode there is a six pages limitation for the
UFROM macro if the AES Key is used for security.
Netlist Resource Report
=======================
CORE Used: 8 Total: 24576 (0.03%)
IO (W/ clocks) Used: 0 Total: 154 (0.00%)
Differential IO Used: 0 Total: 35 (0.00%)
GLOBAL (Chip+Quadrant) Used: 0 Total: 18 (0.00%)
PLL Used: 0 Total: 1 (0.00%)
RAM/FIFO Used: 0 Total: 32 (0.00%)
Low Static ICC Used: 0 Total: 1 (0.00%)
FlashROM Used: 1 Total: 1 (100.00%)
User JTAG Used: 0 Total: 1 (0.00%)
Wrote Verilog netlist to
C:/work/IP/trunk/or1k_startup/syn/flash/smartgen\flash\flash.v.
** Log Ended: Mon Mar 16 11:22:45 2009
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