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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [atlys/] [rtl/] [verilog/] [gpio/] [README] - Rev 677

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GPIO RTL

This is a simple GPIO implementation. It is variable width, however widths of 
multiples of 8 are advised. The first width/8 bytes control are for 
reading/writing to the GPIO registers, the second set of width/8 bytes control 
the direction.

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