OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [libchip/] [serial/] [README.mc68681] - Rev 383

Go to most recent revision | Compare with Previous | Blame | View Log

#
#  $Id: README.mc68681,v 1.2 2001-09-27 12:01:42 chris Exp $
#

Configuration Table Use
=======================

sDeviceName

   The name of this device.

deviceType

   This field must be SERIAL_MC68681.

pDeviceFns

   The device interface control table.  This may be:
      + mc68681_fns for interrupt driven IO
      + mc68681_fns_polled for polled IO

deviceProbe

   This is the address of the routine which probes to see if the device
   is present.

pDeviceFlow

   This field is ignored as hardware flow control is not currently supported.

ulMargin

    This is currently unused.

ulHysteresis

    This is currently unused.

pDeviceParams

    This is set to the default settings.

ulCtrlPort1

   This field is the base address of the entire DUART.

ulCtrlPort2

   This field is the base address of the port specific registers.

ulDataPort

   This field is bit mapped as follows:
     bit 0:  baud rate set a or b
     bit 1-2: BRG selection ("Select Extend bit")

   Note: If both ports on single DUART are not configured for the same
         baud rate set, then unexpected results will occur.

   Note: On the Exar 88c681, if a standard clock of 3.6864 Mhz is used
         and the "Select Extend bit" is 0 (disabled), then the default
         MC68681 baud rate table is selected.

getRegister
setRegister

   These follow standard conventions.

getData
setData

   These are unused since the TX and RX data registers can be accessed
   as regular registers.

ulClock

   This is a pointer to a baud rate mapping table.  If set to
   mc68681_baud_rate_table, then the CSR/ACR/X bit mappings shown
   in the 68681 and 88681 manuals are used.  Otherwise, the board
   specific baud rate mapping is used.

   NULL is not a valid value.

ulIntVector

   This is the interrupt vector number associated with this chip.

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.