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URL https://opencores.org/ocsvn/opentech/opentech/trunk

Subversion Repositories opentech

[/] [opentech/] [web_uploads/] [changes_1_6_0.txt] - Rev 6

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Changes from version 1.5.1

OpenCores.org
======
Site and CVS are Updated

DESIGNS
======
- Free Model Foundation models (updated)
- Gadgetboard (added)
- Logic Analyzer (updated)
- OpenEEG (added)
- OpenHardware.ru projects (addded)
- Gadgetboard (updated)


TOOLS:
=====
In Design Entry
- gEDA (updated)
- TinyCad (updated)
- xcircuit (updated)
- veditor_Eclipse (updated)
- jhdl-ide (added)
- vhdl-emacs-mode (updated)
- KICAD (updated)

In pcb
- FreePCB (updated)
- pcb (added)


In PLDs
- fpgaC (added)


In uC
- ketchlab (updated)
- piklab (added)


In  Analysis
- wcalc (added)
- gsmc+xsmc (added)


In Spice
- ASCO (added)
- gSpiceUI (updated)
- gwave (updated)

In simulation
- Qucs (updated)
- FlowDesign (added)
- gtkwave (updated)


In Synthesis
- balsa (added)

In IC layout/vlsi
- electric (updated)
- magic (updated)
- LayoutEditor (added)
- IRSIM (updated)
- netgen (updated)

In Verification
- confluence (updated)
- hdcaml (added)
- jove (added)

In instruments

In Others


In Verilog
- Covered (updated)
- Ircus (updated)
- verilator (updated)
- veriwell (added)


In VHDL 
- signs (updated)


in ROMs

In Modeling
- GreeSOCs (added)
- sc2ast (added)


In Extras
- Xemacs (updated)
- nedit (updated)
- wincvs (updated)

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