Subversion Repositories opentech

Changes from version 1.6.0

OpenCores.org
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Site and CVS are Updated

DESIGNS
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- Free Model Foundation models (updated)
- simplyrisc (added)
- Gadgetboard (updated)
- freeio (updated)
- vlsitechnology_lib (updated)
- OpenCPU (added)
- Ronja Project (updated)


TOOLS:
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[Analysis]


[Design Entry]
- emacs-modes (updated)
- gEDA (updated)
- hdlmaker (updated)
- KICAD (updated)
- TinyCad (updated)
- veditor_Eclipse (updated)
- xcircuit (updated)


[Instruments]
- qoscc (updated)
- QtDMM (updated)

[Modeling]
- ptolemy (updated)


[pcb]
- gerber2pdf (updated)
- gerbmerge (updated)
- gerbv (updated)
- opencircuit_pcb (updated)
- pcb (updated)


[PLD]
- jhdl (updated)


[ROMs]
- srecords (updated)

[Simulation]
- cider (added)
- Qucs (updated)


[Spice]
- ASCO (updated)
- easyspice (added)
- eispice (added)
- gnucap (updated)
- kjwaves (added)
- pyspice (updated)

[SystemLevel]
- GreenSOCs (updated)
- SystemC-vregs (added)
- SystemPerl (updated)

[Testing]
- pystdf (added)

[uC]
- EVBU (added)
- Sam_I_Am (added)


[Verification]
- jove (updated)


[Verilog]
- Covered (updated)
- dinotrace (updated)
- Icarus (updated)
- ScriptSim (added)
- vbs (updated)
- verilator (updated)
- Verilog-Perl (updated)
- Verilog-Pli (updated)
- VHDL2Vlg (updated)
- voneline (added)


[VHDL]
- signs (updated)
- freehdl (updated)

[VLSI/IC layout]
- Alliance (updated)
- electric (updated)
- IRSIM (updated)
- LayoutEditor (updated)
- magic (updated)
- netgen (updated)
- toped (added)
- xchiplogo (added)



[Synthesis]


[Others]



[Extras]
- Xemacs (updated)
- nedit (updated)
- wincvs (updated)