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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [cache.ld] - Rev 1646
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MEMORY{except : ORIGIN = 0x00000000, LENGTH = 0x00002000flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000}SECTIONS{.reset :{*(.reset)_src_beg = .;} > flash.text :AT ( ADDR (.reset) + SIZEOF (.reset) ){_dst_beg = .;*(.text)} > ram.data :AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) ){*(.data)*(.rodata)_dst_end = .;} > ram.bss :{*(.bss)} > ram.stack ALIGN(0x10) (NOLOAD):{*(.stack)_ram_end = .;} > ram}
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