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[/] [or1k/] [tags/] [rel_1/] [or1200/] [bench/] [monitor.v] - Rev 1783
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////////////////////////////////////////////////////////////////////// //// //// //// OR1200's simulation monitor //// //// //// //// This file is part of the OpenRISC 1200 project //// //// http://www.opencores.org/cores/or1k/ //// //// //// //// Description //// //// Simulation monitor //// //// //// //// To Do: //// //// - move it to bench //// //// //// //// Author(s): //// //// - Damjan Lampret, lampret@opencores.org //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: not supported by cvs2svn $ // Revision 1.1 2001/07/20 00:46:03 lampret // Development version of RTL. Libraries are missing. // // // Enable debug_mem task. Only affects simulation. `define enable_debug_mem // Enable display_arch_state task. Only affects simulation. `define enable_display_arch_state module monitor; task monitortask; begin /* $display("cpu.rfwb_op=%h vip.vipcore.risc.cpu.rf_dataw=%h vip.vipcore.risc.cpu.rf_dataa=%h vip.vipcore.risc.cpu.rf_datab=%h", vip.vipcore.risc.cpu.rfwb_op, vip.vipcore.risc.cpu.rf_dataw, vip.vipcore.risc.cpu.rf_dataa, vip.vipcore.risc.cpu.rf_datab); $display("vip.vipcore.risc.cpu.insn=%h vip.vipcore.risc.cpu.rf_addrw=%h vip.vipcore.risc.cpu.rf_addra=%h vip.vipcore.risc.cpu.rf_addrb=%h vip.vipcore.risc.cpu.simm=%h vip.vipcore.risc.cpu.alu_op=%h vip.vipcore.risc.cpu.branch_op=%h vip.vipcore.risc.cpu.sel_a=%h vip.vipcore.risc.cpu.sel_b=%h", vip.vipcore.risc.cpu.insn, vip.vipcore.risc.cpu.rf_addrw, vip.vipcore.risc.cpu.rf_addra, vip.vipcore.risc.cpu.rf_addrb, vip.vipcore.risc.cpu.simm, vip.vipcore.risc.cpu.alu_op, vip.vipcore.risc.cpu.branch_op, vip.vipcore.risc.cpu.sel_a, vip.vipcore.risc.cpu.sel_b); $display("alu.alu_op=%h alu.comp_op=%h alu.a=%h alu.b=%h alu.result=%h alu.flag_we=%b alu.flag=%b", vip.vipcore.risc.cpu.alu.alu_op, vip.vipcore.risc.cpu.alu.comp_op, vip.vipcore.risc.cpu.alu.a, vip.vipcore.risc.cpu.alu.b, vip.vipcore.risc.cpu.alu.result, vip.vipcore.risc.cpu.alu.flag_we, vip.vipcore.risc.cpu.alu.flag); $display("vip.vipcore.risc.cpu.lsu_op=%h", vip.vipcore.risc.cpu.lsu_op); */ $display(""); end endtask integer fexe; reg [23:0] ref; initial begin ref = 0; fexe = $fopen("executed.log"); $timeformat (-9, 2, " ns", 12); // $shm_open("waves_nedela2.shm"); // $shm_probe(tb_vip, "AS"); // $dumpfile("tb_vip.vcd"); // `include "tb_vip.trace" // $dumpvars(0, tb_vip); // $monitor("TIME %t: dc.dclsu_addr %h", $time, vip.vipcore.risc.dc.dclsu_addr); end task finish_simulation; begin $fclose(fexe); // display_arch_state; display_memory(0, 8191); $shm_save; $shm_close; $dumpflush; $finish; end endtask task caught_sys203; begin $display("simulation terminated due to l.sys 203"); finish_simulation; end endtask /* task display_arch_stateOLD; reg [5:0] i; begin `ifdef enable_display_arch_state $display("Last:"); $display("%h: %h: TIME:%t", risc.cpu.except.wb_pc, risc.cpu.id.wb_insn, $time); $display("PC:"); $write("%h: %h: ", risc.cpu.except.ex_pc, risc.cpu.id.ex_insn); $write(" SR: %h EPCR: %h ESR: %h", risc.cpu.sprs.sr, risc.cpu.except.epcr, risc.cpu.except.esr); for(i = 0; i < 32; i = i + 1) begin if (i % 4 == 0) $display(); $write("GPR%d: %h ", i, risc.cpu.rf.rf_a.mem[i]); end $display("flag: %b", risc.cpu.alu.flag); $display; `endif end endtask */ task display_arch_state; reg [5:0] i; begin `ifdef enable_display_arch_state ref = ref + 1; // if (ref == 17890) begin // $dumpfile("dump.vcd"); // $dumpvars(20,tb_or1200); // end $fwrite(fexe, "\nEXECUTED(): %h: %h", tb_or1200.risc.cpu.except.wb_pc, tb_or1200.risc.cpu.id.wb_insn); for(i = 0; i < 32; i = i + 1) begin if (i % 4 == 0) $fdisplay(fexe); $fwrite(fexe, "GPR%d: %h ", i, tb_or1200.risc.cpu.rf.rf_a.mem[i]); end $fdisplay(fexe); `endif end endtask task display_memory; input [31:0] from; input [31:0] to; integer i; begin // for(i = from; i < to; i = i + 4) // $display("mem[%h] = %h mem[%h] = %h mem[%h] = %h mem[%h] = %h ", // i, sram2.ramCore[i], i+4, sram2.ramCore[i+1], i+8, sram2.ramCore[i+2], i+12, sram2.ramCore[i+3]); //zSramX32 // i<<2, sram2.mem[i], (i<<2)+4, sram2.mem[i+1], (i<<2)+8, sram2.mem[i+2], (i<<2)+12, sram2.mem[i+3]); //sram32kx32 end endtask task debug_mem; input [79:0] device; input write; input [31:0] addr; input [31:0] data; input [3:0] bs; begin `ifdef enable_debug_mem if (write) $display( "%t: WRITE to %s addr 0x%h with a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs); else $display( "%t: READ from %s addr 0x%h which contains a value of 0x%h using byte enables of 'b%b", $time, device, addr, data, bs); `endif end endtask always @(posedge tb_or1200.risc.cpu.id.clk) if (!tb_or1200.risc.cpu.id.pipeline_freeze) begin #3; if ((tb_or1200.risc.cpu.id.wb_insn != 32'h1500ffff) && (tb_or1200.risc.cpu.id.wb_insn != 32'h14000000)) display_arch_state; if (tb_or1200.risc.cpu.id.ex_insn == 32'h200000cb) // small hack to stop simulation (l.sys 203) caught_sys203; end endmodule
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