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Feb 10,2010
RTL - Update to the WISHBONE interface when wait states are enabled to trade 16 data flops for 3 address registers. This change now also requires single cycle timing on the WISHBONE address bus, multi-cycle timing is still allowed on the WISHBONE write data bus. In the old design WISHBONE read cycles required the address to be decoded and the read data to be latched in the first cycle and the there was a whole cycle to drive the read data bus. The new design latches the address in the first cycle then decodes the address and outputs the data in the second cycle. (The WISHBONE bus doesn't require the address or data to be latched for multi-cycle operation but by doing this it is hoped some power will be saved in the combinational logic by reducing the decoding activity at each address change.)

Testbench - Minor change to add parameter to pit instance.

Doc -

July 31, 2011
Added rtl/sys_verilog and bench/verilog/sys_verilog directories. This is the first pass at an upgrade to System Verilog. The changes were to uses new types, "logic" and "bit", new always blocks, "always_ff "and "always_comb", and ".*" for signal name passing. 

Oct 24, 2011
Updated the rtl/sys_verilog directory to include a Wishbone "interface". The bench/sys_verilog was also updated to include the Wishbone interface. Because there are four different instances of the pit module(based on i/o connections and parameters) the test bench required four different instances of the Wishbone interface to connect each pit instance. Because of this there was no significant reduction in the lines of code required in the testbench, and shows some of the pitfalls to be encountered when you get outside of the box of using interfaces as taught in class examples.