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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2017 Authors and OPENCORES.ORG                 ////
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//// This source file may be used and distributed without         ////
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//// removed from the file and that any derivative work contains  ////
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//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//////////////////////////////////////////////////////////////////////


module tb_top();

  // --------------------------------------------------------------------
  // test bench clock & reset
  wire clk_100mhz;
  wire tb_clk = clk_100mhz;
  wire tb_rst;

  tb_base #(.PERIOD(10_000)) tb(clk_100mhz, tb_rst);


  // --------------------------------------------------------------------
  //
  wire tb_rst_s;
  wire aclk     = tb_clk;
  wire aresetn  = ~tb_rst_s;

  sync_reset sync_reset_i(tb_clk, tb_rst, tb_rst_s);


  // --------------------------------------------------------------------
  //
  import tb_chnl_convolution_pkg::*;


  // --------------------------------------------------------------------
  //
  riffa_chnl_if #(.N(N)) chnl_bus();


  // --------------------------------------------------------------------
  //
        wire CLK = tb_clk;
        wire RST = tb_rst_s;
  assign chnl_bus.rx_clk = CLK;
  assign chnl_bus.tx_clk = CLK;

  chnl_convolution #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
    dut
    (
      .CHNL_RX_CLK(chnl_bus.rx_clk),
      .CHNL_RX(chnl_bus.rx),
      .CHNL_RX_ACK(chnl_bus.rx_ack),
      .CHNL_RX_LAST(chnl_bus.rx_last),
      .CHNL_RX_LEN(chnl_bus.rx_len),
      .CHNL_RX_OFF(chnl_bus.rx_off),
      .CHNL_RX_DATA(chnl_bus.rx_data),
      .CHNL_RX_DATA_VALID(chnl_bus.rx_data_valid),
      .CHNL_RX_DATA_REN(chnl_bus.rx_data_ren),
      .CHNL_TX_CLK(chnl_bus.tx_clk),
      .CHNL_TX(chnl_bus.tx),
      .CHNL_TX_ACK(chnl_bus.tx_ack),
      .CHNL_TX_LAST(chnl_bus.tx_last),
      .CHNL_TX_LEN(chnl_bus.tx_len),
      .CHNL_TX_OFF(chnl_bus.tx_off),
      .CHNL_TX_DATA(chnl_bus.tx_data),
      .CHNL_TX_DATA_VALID(chnl_bus.tx_data_valid),
      .CHNL_TX_DATA_REN(chnl_bus.tx_data_ren),
      .*
    );


  // --------------------------------------------------------------------
  //
  tb_chnl_convolution_class #(.N(N)) a_h;

  initial
    a_h = new(chnl_bus);


  // --------------------------------------------------------------------
  // sim models
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // \|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/-\|/
  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '

  // --------------------------------------------------------------------
  //
  int rx_count = 0;
  wire rx_en = chnl_bus.rx_data_valid & chnl_bus.rx_data_ren;

  always_ff @(posedge chnl_bus.tx_clk)
    if(chnl_bus.rx)
    begin
      if(rx_en)
        rx_count++;
    end
    else
      rx_count = 0;


  // --------------------------------------------------------------------
  //
  int tx_count = 0;
  wire tx_en = chnl_bus.tx_data_valid & chnl_bus.tx_data_ren;

  always_ff @(posedge chnl_bus.tx_clk)
    if(chnl_bus.tx)
    begin
      if(tx_en)
        tx_count++;
    end
    else
      tx_count = 0;



  //  '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '   '
  // /|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\-/|\
  //  |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |   |
  // sim models
  // --------------------------------------------------------------------



  // --------------------------------------------------------------------
  // test
  the_test test( tb_clk, tb_rst );

  initial
    begin

      test.run_the_test();

      $display("^^^---------------------------------");
      $display("^^^ %16.t | Testbench done.", $time);
      $display("^^^---------------------------------");

      $display("^^^---------------------------------");

      $stop();

    end

endmodule