page5
RISE - Notes
1/2
21. November 2006
Christian Walter
Pipeline
If a write to PC is detected then the branch signal is generated. In this case the content of the pipeline
in the IF/ID and ID/EX is cleared.
If a operation is conditional it must be stalled until the previous SR is available in the register file.
A pipeline stage which stalls its predecessors must change its current output value to NOP because otherweise
the next stages would execute the current instruction more than once. This is done by asserting the stall_out
signal.
If stall_in is asserted a pipeline stage musst hold its current output value. A stalled pipeline stage should not
consume any resources (locking registers, ...)
If the clear input signal is asserted the output must be reset to OPCODE_NOP.