GRLIB=../..
TOP=t1sp
BOARD=altera-ep2s60-ddr
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
EFFORT=std
XSTOPT=""
SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -verification_mode 1; set_option -write_apr_constraint 0"
VHDLSYNFILES=config.vhd ahbrom.vhd smc_mctrl.vhd t1sp.vhd 
VHDLSIMFILES=testbench.vhd
SIMTOP=testbench
SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
#CLEAN=soft-clean

# T1 options
VLOGOPT=+define+RTL_SPARC0 +define+FPGA_SYN +define+FPGA_SYN_1THREAD +define+FPGA_SYN_NO_SPU
SYNPVLOGDEFS="FPGA_SYN FPGA_SYN_1THREAD FPGA_SYN_NO_SPU"
NCVLOGOPT="-define FPGA_SYN -define FPGA_SYN_1THREAD -define FPGA_SYN_NO_SPU"

LIBADD = sun

TECHLIBS = altera altera_mf stratixii
LIBSKIP = gsi spansion fmf core1553bbc core1553brm core1553brt gr1553 corePCIF \
	tmtc openchip ihp gleichmann spw eth hynix
DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \
	spacewire usb greth net haps ac97 slink ascs fpu coremp7 hcan
FILESKIP = grcan.vhd

#include $(GRLIB)/software/leon3/Makefile
include $(GRLIB)/bin/Makefile


##################  project specific targets ##########################

