GRLIB=../..
TOP=t1sp
BOARD=gr-cpci-xc2v
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
#UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
UCF=$(GRLIB)/boards/$(BOARD)/leon3mp.ucf
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
EFFORT=med
XSTOPT=""
ISEMAPOPT=""
VHDLSYNFILES=config.vhd sdmctrl.vhd mctrl.vhd t1sp.vhd
VHDLSIMFILES=testbench.vhd
SIMTOP=testbench
#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
SDCFILE=default.sdc
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
#CLEAN=soft-clean

# T1 options
#VLOGOPT="+define+RTL_SPARC0 +define+FPGA_SYN_1THREAD +define+FPGA_SYN_NO_SPU"
VLOGOPT=+define+RTL_SPARC0 +define+FPGA_SYN +define+FPGA_SYN_1THREAD +define+FPGA_SYN_NO_SPU
SYNPVLOGDEFS="FPGA_SYN FPGA_SYN_1THREAD FPGA_SYN_NO_SPU"
NCVLOGOPT="-define FPGA_SYN -define FPGA_SYN_1THREAD -define FPGA_SYN_NO_SPU"

LIBADD = sun
TECHLIBS = unisim
LIBSKIP = gsi fmf spansion core1553bbc core1553brm core1553brt gr1553 corePCIF \
	tmtc openchip hynix cypress ihp gleichmann spw opencores 

DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata leon3ft i2c \
	can hcan spacewire fpu ascs slink coremp7

FILESKIP = i2cmst.vhd

include $(GRLIB)/bin/Makefile
#include $(GRLIB)/software/t1/Makefile


##################  project specific targets ##########################

#	cpp -P prom.S | sparc64-elf-as -o tmp.o
soft64: prom.S prom.h
	cpp -P prom.S | ./g_as -o tmp.o
	sparc64-elf-ld tmp.o -o tmp -Ttext=0xfff00000
	sparc64-elf-strip tmp
	sparc64-elf-objcopy -O srec tmp prom.srec
