../../bin/route t1sp ../../boards/gr-cpci-xc4v/leon3mp.ucf xc4vlx100-ff1513-10 high ../../boards/gr-cpci-xc4v/default.ut synplify \
	../../netlists/xilinx/virtex4 
edif2ngd synplify/t1sp.edf
Release 9.2.04i - edif2ngd J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 9.2.04i edif2ngd J.40
INFO:NgdBuild - Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
Applying constraints in "synplify/t1sp.ncf" to module "t1sp"...
Writing module to "t1sp.ngo"...
ngdbuild t1sp.ngo -aul -uc ../../boards/gr-cpci-xc4v/leon3mp.ucf -p xc4vlx100-ff1513-10 -sd ../../netlists/xilinx/virtex4
Release 9.2.04i - ngdbuild J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild t1sp.ngo -aul -uc ../../boards/gr-cpci-xc4v/leon3mp.ucf
-p xc4vlx100-ff1513-10 -sd ../../netlists/xilinx/virtex4

Launcher: The source netlist for "t1sp.ngo" was not found; the current NGO file
will be used and no new NGO description will be compiled.  This probably means
that the source netlist was moved or deleted.
Reading NGO file "/home/jiri/ibm/vhdl/grlib/designs/t1-gr-cpci-xc4v/t1sp.ngo"
...

Applying constraints in "../../boards/gr-cpci-xc4v/leon3mp.ucf" to the design...
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 22: Could not
   find net(s) 'spw_clk' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:751 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 30': Could not
   find instance(s) 'clkgen0_xc2v_v_dll0' in the design.  The 'Allow Unmatched
   LOC Constraints' ISE property is set ( -aul switch ) so this constraint will
   be ignored.
INFO:NgdBuild:751 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 31': Could not
   find instance(s) 'clkgen0_xc2v_v_sd0_dll1' in the design.  The 'Allow
   Unmatched LOC Constraints' ISE property is set ( -aul switch ) so this
   constraint will be ignored.
INFO:NgdBuild:751 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 32': Could not
   find instance(s) 'clkgen0/xc2v_v_clk2xgen_dll2x' in the design.  The 'Allow
   Unmatched LOC Constraints' ISE property is set ( -aul switch ) so this
   constraint will be ignored.
INFO:NgdBuild:751 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 37': Could not
   find instance(s) 'clkgen0/xc2v.v/clk2xgen.dll2x' in the design.  The 'Allow
   Unmatched LOC Constraints' ISE property is set ( -aul switch ) so this
   constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 102: Could not
   find net(s) 'cb(0)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 103: Could not
   find net(s) 'cb(1)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 104: Could not
   find net(s) 'cb(2)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 105: Could not
   find net(s) 'cb(3)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 106: Could not
   find net(s) 'cb(4)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 107: Could not
   find net(s) 'cb(5)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 108: Could not
   find net(s) 'cb(6)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 109: Could not
   find net(s) 'cb(7)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 136: Could not
   find net(s) 'bexcn' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 137: Could not
   find net(s) 'brdyn' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 139: Could not
   find net(s) 'wdogn' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 201: Could not
   find net(s) 'scb(0)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 202: Could not
   find net(s) 'scb(1)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 203: Could not
   find net(s) 'scb(2)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 204: Could not
   find net(s) 'scb(3)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 205: Could not
   find net(s) 'scb(4)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 206: Could not
   find net(s) 'scb(5)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 207: Could not
   find net(s) 'scb(6)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 208: Could not
   find net(s) 'scb(7)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 237: Could not
   find net(s) 'sdcke(2)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 238: Could not
   find net(s) 'sdcke(3)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 242: Could not
   find net(s) 'sdcsn(2)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 243: Could not
   find net(s) 'sdcsn(3)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 258: Could not
   find net(s) 'sdscl' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 259: Could not
   find net(s) 'sdsda(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 260: Could not
   find net(s) 'sdsda(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 282: Could not
   find net(s) 'emdint' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 324: Could not
   find net(s) 'pci_ad(32)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 325: Could not
   find net(s) 'pci_ad(33)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 326: Could not
   find net(s) 'pci_ad(34)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 327: Could not
   find net(s) 'pci_ad(35)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 328: Could not
   find net(s) 'pci_ad(36)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 329: Could not
   find net(s) 'pci_ad(37)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 330: Could not
   find net(s) 'pci_ad(38)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 331: Could not
   find net(s) 'pci_ad(39)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 332: Could not
   find net(s) 'pci_ad(40)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 333: Could not
   find net(s) 'pci_ad(41)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 334: Could not
   find net(s) 'pci_ad(42)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 335: Could not
   find net(s) 'pci_ad(43)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 336: Could not
   find net(s) 'pci_ad(44)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 337: Could not
   find net(s) 'pci_ad(45)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 338: Could not
   find net(s) 'pci_ad(46)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 339: Could not
   find net(s) 'pci_ad(47)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 340: Could not
   find net(s) 'pci_ad(48)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 341: Could not
   find net(s) 'pci_ad(49)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 342: Could not
   find net(s) 'pci_ad(50)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 343: Could not
   find net(s) 'pci_ad(51)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 344: Could not
   find net(s) 'pci_ad(52)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 345: Could not
   find net(s) 'pci_ad(53)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 346: Could not
   find net(s) 'pci_ad(54)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 347: Could not
   find net(s) 'pci_ad(55)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 348: Could not
   find net(s) 'pci_ad(56)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 349: Could not
   find net(s) 'pci_ad(57)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 350: Could not
   find net(s) 'pci_ad(58)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 351: Could not
   find net(s) 'pci_ad(59)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 352: Could not
   find net(s) 'pci_ad(60)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 353: Could not
   find net(s) 'pci_ad(61)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 354: Could not
   find net(s) 'pci_ad(62)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 355: Could not
   find net(s) 'pci_ad(63)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 360: Could not
   find net(s) 'pci_cbe(4)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 361: Could not
   find net(s) 'pci_cbe(5)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 362: Could not
   find net(s) 'pci_cbe(6)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 363: Could not
   find net(s) 'pci_cbe(7)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 367: Could not
   find net(s) 'pci64en' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 369: Could not
   find net(s) 'pci_ack64n' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 379: Could not
   find net(s) 'pci_arb_gnt(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 380: Could not
   find net(s) 'pci_arb_gnt(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 381: Could not
   find net(s) 'pci_arb_gnt(6)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 382: Could not
   find net(s) 'pci_arb_gnt(7)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 388: Could not
   find net(s) 'pci_arb_req(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 389: Could not
   find net(s) 'pci_arb_req(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 390: Could not
   find net(s) 'pci_arb_req(6)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 391: Could not
   find net(s) 'pci_arb_req(7)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 397: Could not
   find net(s) 'pci_par64' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 399: Could not
   find net(s) 'pci_req64n' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 400: Could not
   find net(s) 'pci_arb_req' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 407: Could not
   find net(s) 'led(1)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 408: Could not
   find net(s) 'led(2)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 409: Could not
   find net(s) 'led(3)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 412: Could not
   find net(s) 'xd(0)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 413: Could not
   find net(s) 'xd(1)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 414: Could not
   find net(s) 'xd(2)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 415: Could not
   find net(s) 'xd(3)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 416: Could not
   find net(s) 'xd(4)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 417: Could not
   find net(s) 'xd(5)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 418: Could not
   find net(s) 'xd(6)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 419: Could not
   find net(s) 'xd(7)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 434: Could not
   find net(s) 'spw_rxdp(0)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 435: Could not
   find net(s) 'spw_rxdn(0)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 437: Could not
   find net(s) 'spw_txsp(0)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 438: Could not
   find net(s) 'spw_txsn(0)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 440: Could not
   find net(s) 'spw_rxsp(0)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 441: Could not
   find net(s) 'spw_rxsn(0)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 443: Could not
   find net(s) 'spw_txdp(0)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 444: Could not
   find net(s) 'spw_txdn(0)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 446: Could not
   find net(s) 'spw_rxdp(1)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 447: Could not
   find net(s) 'spw_rxdn(1)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 449: Could not
   find net(s) 'spw_txsp(1)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 450: Could not
   find net(s) 'spw_txsn(1)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 452: Could not
   find net(s) 'spw_rxsp(1)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 453: Could not
   find net(s) 'spw_rxsn(1)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 455: Could not
   find net(s) 'spw_txdp(1)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 456: Could not
   find net(s) 'spw_txdn(1)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 458: Could not
   find net(s) 'spw_rxdp(2)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 459: Could not
   find net(s) 'spw_rxdn(2)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 461: Could not
   find net(s) 'spw_rxsp(2)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 462: Could not
   find net(s) 'spw_rxsn(2)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 464: Could not
   find net(s) 'spw_txsp(2)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 465: Could not
   find net(s) 'spw_txsn(2)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 467: Could not
   find net(s) 'spw_txdp(2)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 468: Could not
   find net(s) 'spw_txdn(2)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 470: Could not
   find net(s) 'spw_rxdp(3)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 471: Could not
   find net(s) 'spw_rxdn(3)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 473: Could not
   find net(s) 'spw_rxsp(3)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 474: Could not
   find net(s) 'spw_rxsn(3)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 476: Could not
   find net(s) 'spw_txsp(3)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 477: Could not
   find net(s) 'spw_txsn(3)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 479: Could not
   find net(s) 'spw_txdp(3)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 480: Could not
   find net(s) 'spw_txdn(3)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 482: Could not
   find net(s) 'spw_rxdp(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 483: Could not
   find net(s) 'spw_rxdn(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 485: Could not
   find net(s) 'spw_txdp(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 486: Could not
   find net(s) 'spw_txdn(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 488: Could not
   find net(s) 'spw_rxsp(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 489: Could not
   find net(s) 'spw_rxsn(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 491: Could not
   find net(s) 'spw_txsp(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 492: Could not
   find net(s) 'spw_txsn(4)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 494: Could not
   find net(s) 'spw_rxdp(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 495: Could not
   find net(s) 'spw_rxdn(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 497: Could not
   find net(s) 'spw_txdp(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 498: Could not
   find net(s) 'spw_txdn(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 500: Could not
   find net(s) 'spw_rxsp(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 501: Could not
   find net(s) 'spw_rxsn(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 503: Could not
   find net(s) 'spw_txsp(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 504: Could not
   find net(s) 'spw_txsn(5)' in the design. The 'Allow Unmatched LOC
   Constraints' ISE option is set ( -aul switch ) so this constraint will be
   ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 517: Could not
   find net(s) 'gpio(8)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 518: Could not
   find net(s) 'gpio(9)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 519: Could not
   find net(s) 'gpio(10)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 520: Could not
   find net(s) 'gpio(11)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 521: Could not
   find net(s) 'gpio(12)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 522: Could not
   find net(s) 'gpio(13)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 523: Could not
   find net(s) 'gpio(14)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 524: Could not
   find net(s) 'gpio(15)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 527: Could not
   find net(s) 'cts2' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 528: Could not
   find net(s) 'rts2' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 531: Could not
   find net(s) 'cts1' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 532: Could not
   find net(s) 'rts1' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 537: Could not
   find net(s) 'adcn(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 538: Could not
   find net(s) 'adcn(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 539: Could not
   find net(s) 'adcn(2)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 540: Could not
   find net(s) 'adcn(3)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 541: Could not
   find net(s) 'adcn(4)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 542: Could not
   find net(s) 'adcn(5)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 543: Could not
   find net(s) 'adcn(6)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 544: Could not
   find net(s) 'adcn(7)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 546: Could not
   find net(s) 'adcp(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 547: Could not
   find net(s) 'adcp(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 548: Could not
   find net(s) 'adcp(2)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 549: Could not
   find net(s) 'adcp(3)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 550: Could not
   find net(s) 'adcp(4)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 551: Could not
   find net(s) 'adcp(5)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 552: Could not
   find net(s) 'adcp(6)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 553: Could not
   find net(s) 'adcp(7)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 555: Could not
   find net(s) 'smn(0)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 556: Could not
   find net(s) 'smn(1)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 557: Could not
   find net(s) 'smn(2)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 558: Could not
   find net(s) 'smn(3)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 559: Could not
   find net(s) 'smn(4)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 560: Could not
   find net(s) 'smn(5)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 561: Could not
   find net(s) 'smn(6)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 562: Could not
   find net(s) 'smn(7)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 564: Could not
   find net(s) 'smp(0)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 565: Could not
   find net(s) 'smp(1)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 566: Could not
   find net(s) 'smp(2)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 567: Could not
   find net(s) 'smp(3)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 568: Could not
   find net(s) 'smp(4)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 569: Could not
   find net(s) 'smp(5)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 570: Could not
   find net(s) 'smp(6)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 571: Could not
   find net(s) 'smp(7)' in the design. The 'Allow Unmatched LOC Constraints' ISE
   option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 574: Could not
   find net(s) 'genio(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 575: Could not
   find net(s) 'genio(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 576: Could not
   find net(s) 'genio(2)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 577: Could not
   find net(s) 'genio(3)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 578: Could not
   find net(s) 'genio(4)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 579: Could not
   find net(s) 'genio(5)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 580: Could not
   find net(s) 'genio(6)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 581: Could not
   find net(s) 'genio(7)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 582: Could not
   find net(s) 'genio(8)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 583: Could not
   find net(s) 'genio(9)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 584: Could not
   find net(s) 'genio(10)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 585: Could not
   find net(s) 'genio(11)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 586: Could not
   find net(s) 'genio(12)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 588: Could not
   find net(s) 'genio(14)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 591: Could not
   find net(s) 'can_rxd(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 592: Could not
   find net(s) 'can_rxd(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 593: Could not
   find net(s) 'can_txd(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 594: Could not
   find net(s) 'can_txd(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 596: Could not
   find net(s) 'genio(16)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 597: Could not
   find net(s) 'genio(17)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 598: Could not
   find net(s) 'genio(18)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 599: Could not
   find net(s) 'genio(19)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 600: Could not
   find net(s) 'genio(20)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 601: Could not
   find net(s) 'genio(21)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 602: Could not
   find net(s) 'genio(22)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 603: Could not
   find net(s) 'genio(23)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 604: Could not
   find net(s) 'genio(24)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 605: Could not
   find net(s) 'genio(25)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 606: Could not
   find net(s) 'genio(26)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 607: Could not
   find net(s) 'genio(27)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 608: Could not
   find net(s) 'genio(28)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 609: Could not
   find net(s) 'genio(29)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 610: Could not
   find net(s) 'genio(30)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 611: Could not
   find net(s) 'genio(31)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 612: Could not
   find net(s) 'genio(32)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 613: Could not
   find net(s) 'genio(33)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 614: Could not
   find net(s) 'genio(34)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 615: Could not
   find net(s) 'genio(35)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 616: Could not
   find net(s) 'genio(36)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 617: Could not
   find net(s) 'genio(37)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 618: Could not
   find net(s) 'genio(38)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 619: Could not
   find net(s) 'genio(39)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 620: Could not
   find net(s) 'genio(40)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 621: Could not
   find net(s) 'genio(41)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 622: Could not
   find net(s) 'genio(42)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 623: Could not
   find net(s) 'genio(43)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 624: Could not
   find net(s) 'genio(44)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 625: Could not
   find net(s) 'genio(45)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 626: Could not
   find net(s) 'genio(46)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 627: Could not
   find net(s) 'genio(47)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 629: Could not
   find net(s) 'genio(48)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 630: Could not
   find net(s) 'genio(49)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 631: Could not
   find net(s) 'genio(50)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 632: Could not
   find net(s) 'genio(51)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 633: Could not
   find net(s) 'genio(52)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 634: Could not
   find net(s) 'genio(53)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 635: Could not
   find net(s) 'genio(54)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 636: Could not
   find net(s) 'genio(55)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 637: Could not
   find net(s) 'genio(56)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 638: Could not
   find net(s) 'genio(57)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 639: Could not
   find net(s) 'genio(58)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 640: Could not
   find net(s) 'genio(59)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 642: Could not
   find net(s) 'genio(61)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 644: Could not
   find net(s) 'genio(63)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 646: Could not
   find net(s) 'genio(64)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 647: Could not
   find net(s) 'genio(65)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 648: Could not
   find net(s) 'genio(66)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 649: Could not
   find net(s) 'genio(67)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 650: Could not
   find net(s) 'genio(68)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 651: Could not
   find net(s) 'genio(69)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 652: Could not
   find net(s) 'genio(70)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 653: Could not
   find net(s) 'genio(71)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 654: Could not
   find net(s) 'genio(72)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 655: Could not
   find net(s) 'genio(73)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 656: Could not
   find net(s) 'genio(74)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 657: Could not
   find net(s) 'genio(75)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 658: Could not
   find net(s) 'genio(76)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 659: Could not
   find net(s) 'genio(77)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 660: Could not
   find net(s) 'genio(78)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 661: Could not
   find net(s) 'genio(79)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 712: Could not
   find net(s) 'genio(128)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 713: Could not
   find net(s) 'genio(129)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 714: Could not
   find net(s) 'genio(130)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 715: Could not
   find net(s) 'genio(131)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 717: Could not
   find net(s) 'genio(132)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 718: Could not
   find net(s) 'genio(133)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 719: Could not
   find net(s) 'genio(134)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 720: Could not
   find net(s) 'genio(135)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 721: Could not
   find net(s) 'genio(136)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 722: Could not
   find net(s) 'genio(137)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 723: Could not
   find net(s) 'genio(138)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 724: Could not
   find net(s) 'genio(139)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 725: Could not
   find net(s) 'genio(140)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 726: Could not
   find net(s) 'genio(141)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 727: Could not
   find net(s) 'genio(142)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 728: Could not
   find net(s) 'genio(143)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 729: Could not
   find net(s) 'genio(144)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 730: Could not
   find net(s) 'genio(145)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 731: Could not
   find net(s) 'genio(146)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 732: Could not
   find net(s) 'genio(147)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 733: Could not
   find net(s) 'genio(148)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 734: Could not
   find net(s) 'genio(149)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 735: Could not
   find net(s) 'genio(150)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 736: Could not
   find net(s) 'genio(151)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 737: Could not
   find net(s) 'genio(152)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 738: Could not
   find net(s) 'genio(153)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 739: Could not
   find net(s) 'genio(154)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 740: Could not
   find net(s) 'genio(155)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 741: Could not
   find net(s) 'genio(156)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 742: Could not
   find net(s) 'genio(157)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 743: Could not
   find net(s) 'genio(158)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 744: Could not
   find net(s) 'genio(159)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 746: Could not
   find net(s) 'genio(160)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 747: Could not
   find net(s) 'genio(161)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 748: Could not
   find net(s) 'genio(162)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 749: Could not
   find net(s) 'genio(163)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 750: Could not
   find net(s) 'genio(164)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 751: Could not
   find net(s) 'genio(165)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 752: Could not
   find net(s) 'genio(166)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 753: Could not
   find net(s) 'genio(167)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 755: Could not
   find net(s) 'genio(168)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 756: Could not
   find net(s) 'genio(169)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 757: Could not
   find net(s) 'genio(170)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 758: Could not
   find net(s) 'genio(171)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 759: Could not
   find net(s) 'genio(172)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 760: Could not
   find net(s) 'genio(173)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 761: Could not
   find net(s) 'genio(174)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 762: Could not
   find net(s) 'genio(175)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 764: Could not
   find net(s) 'pciga(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 765: Could not
   find net(s) 'pciga(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 766: Could not
   find net(s) 'pciga(2)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 767: Could not
   find net(s) 'pciga(3)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 768: Could not
   find net(s) 'pciga(4)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 771: Could not
   find net(s) 'spw_ren(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 772: Could not
   find net(s) 'spw_ren(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 773: Could not
   find net(s) 'spw_ten(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 774: Could not
   find net(s) 'spw_ten(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 776: Could not
   find net(s) 'spw_rxd(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 777: Could not
   find net(s) 'spw_rxd(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 778: Could not
   find net(s) 'spw_rxs(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 779: Could not
   find net(s) 'spw_rxs(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 780: Could not
   find net(s) 'spw_txs(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 781: Could not
   find net(s) 'spw_txs(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 782: Could not
   find net(s) 'spw_txd(0)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.
INFO:NgdBuild:754 - "../../boards/gr-cpci-xc4v/leon3mp.ucf" Line 783: Could not
   find net(s) 'spw_txd(1)' in the design. The 'Allow Unmatched LOC Constraints'
   ISE option is set ( -aul switch ) so this constraint will be ignored.

Checking timing specifications ...
INFO:XdmHelpers:851 - TNM "clk", used in period specification "TS_clk", was
   traced into DCM_ADV instance "clkgen0/xc2v.v/dll0/DCM_ADV". The following new
   TNM groups and period specifications were generated at the DCM_ADV output(s):
   CLKFX: TS_clkgen0_xc2v_v_clk0B=PERIOD clkgen0_xc2v_v_clk0B TS_clk/0.7 HIGH
50%
INFO:XdmHelpers:851 - TNM "clkgen0_xc2v_v_clk0B", used in period specification
   "TS_clkgen0_xc2v_v_clk0B", was traced into DCM_ADV instance
   "clkgen0/xc2v.v/sd0.dll1/DCM_ADV". The following new TNM groups and period
   specifications were generated at the DCM_ADV output(s):
   <none> (no matching synchronous elements driven by DCM_ADV outputs)
Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "t1sp.ngd" ...

Writing NGDBUILD log file "t1sp.bld"...

NGDBUILD done.
map -pr b -ol high -p xc4vlx100-ff1513-10 t1sp
Release 9.2.04i - Map J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
Using target part "4vlx100ff1513-10".
Mapping design into LUTs...
Writing file t1sp.ngm...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Writing design file "t1sp.ncd"...

Design Summary:
Number of errors:      0
Number of warnings:  166
Logic Utilization:
  Number of Slice Flip Flops:      20,891 out of  98,304   21%
  Number of 4 input LUTs:          39,698 out of  98,304   40%
Logic Distribution:
  Number of occupied Slices:                       29,210 out of  49,152   59%
    Number of Slices containing only related logic:  29,210 out of  29,210  100%
    Number of Slices containing unrelated logic:          0 out of  29,210    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         47,109 out of  98,304   47%
  Number used as logic:             39,698
  Number used as a route-thru:         444
  Number used for Dual Port RAMs:    6,860
    (Two LUTs used per Dual Port RAM)
  Number used for 32x1 RAMs:            72
    (Two LUTs used per 32x1 RAM)
  Number used as Shift registers:       35
  Number of bonded IOBs:              274 out of     960   28%
  Number of BUFG/BUFGCTRLs:             4 out of      32   12%
    Number used as BUFGs:                4
    Number used as BUFGCTRLs:            0
  Number of FIFO16/RAMB16s:            47 out of     240   19%
    Number used as FIFO16s:              0
    Number used as RAMB16s:             47
  Number of DSP48s:                     8 out of      96    8%
  Number of DCM_ADVs:                   2 out of      12   16%
  Number of BSCAN_VIRTEX4s:             2 out of       4   50%

Total equivalent gate count for design:  3,960,164
Additional JTAG gate count for IOBs:  13,152
Peak Memory Usage:  630 MB
Total REAL time to MAP completion:  2 mins 36 secs 
Total CPU time to MAP completion:   2 mins 34 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "t1sp.mrp" for details.
par -ol high -pl high -w t1sp t1sp.ncd
Release 9.2.04i - par J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.


WARNING:Par:69 - Option -pl overrides some effects of -ol.

Constraints file: t1sp.pcf.
Loading device for application Rf_Device from file '4vlx100.nph' in environment /usr/local/xilinx/ise92i01.
   "t1sp" is an NCD, version 3.1, device xc4vlx100, package ff1513, speed -10
The STEPPING level for this design is 0.

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:3224 - The clock pci_clk associated with OFFSET = OUT 11 ns AFTER COMP "pci_clk"; does not clock any
   registered output components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 11 ns AFTER COMP "pci_clk"; ignored during timing analysis
WARNING:Timing:3224 - The clock pci_clk associated with OFFSET = IN 7 ns BEFORE COMP "pci_clk"; does not clock any
   registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 7 ns BEFORE COMP "pci_clk"; ignored during timing analysis

Device speed data version:  "PRODUCTION 1.68 2007-11-08".


Device Utilization Summary:

   Number of BSCANs                          2 out of 4      50%
   Number of BUFGs                           4 out of 32     12%
   Number of DCM_ADVs                        2 out of 12     16%
      Number of LOCed DCM_ADVs               2 out of 2     100%

   Number of DSP48s                          8 out of 96      8%
   Number of ILOGICs                       107 out of 960    11%
   Number of External IOBs                 274 out of 960    28%
      Number of LOCed IOBs                 274 out of 274   100%

   Number of OLOGICs                       175 out of 960    18%
   Number of RAMB16s                        47 out of 240    19%
   Number of Slices                      29210 out of 49152  59%
      Number of SLICEMs                   3892 out of 24576  15%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 1 mins 5 secs 
Finished initial Timing Analysis.  REAL time: 1 mins 8 secs 

WARNING:Par:288 - The signal gpio(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal gpio(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal gpio(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal gpio(3)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal gpio(4)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal gpio(5)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal gpio(6)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal gpio(7)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dsuen_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dsurx_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_clk_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_gnt_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_par_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_req_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_rst_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(3)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(4)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(5)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(6)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(7)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(8)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(9)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_idsel_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_frame_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_66_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal dsubre_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_lock_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_irdy_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_host_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_perr_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_serr_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_trdy_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_stop_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(10)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(11)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(12)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(20)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(13)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(21)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(14)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(22)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(30)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(15)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(23)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(31)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(16)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(24)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(17)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(25)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(18)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(26)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(19)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(27)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(28)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_ad(29)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_cbe(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_cbe(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_cbe(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_cbe(3)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_arb_req(0)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_arb_req(1)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_arb_req(2)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_arb_req(3)_IBUF has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal pci_devsel_IBUF has no load.  PAR will not attempt to route this signal.

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:a659ff) REAL time: 2 mins 7 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 2 mins 8 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 2 mins 8 secs 

Phase 4.2
.
Phase 4.2 (Checksum:26259fc) REAL time: 4 mins 54 secs 

Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 4 mins 54 secs 

Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 4 mins 55 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 4 mins 57 secs 

Phase 8.8
..................................................
.....................................................................................................................................................................................
..........................................................................................................................................................................................................................
.............................................................................................................................................................................
..........................................................................................................................................................................
...
Phase 8.8 (Checksum:90bfa50) REAL time: 26 mins 30 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 26 mins 33 secs 

Phase 11.18
Phase 11.18 (Checksum:68e7775) REAL time: 34 mins 59 secs 

Phase 12.27
Phase 12.27 (Checksum:7270df4) REAL time: 35 mins 9 secs 

Phase 13.5
Phase 13.5 (Checksum:7bfa473) REAL time: 35 mins 12 secs 

Phase 15.34
Phase 15.34 (Checksum:8f0d171) REAL time: 35 mins 12 secs 

REAL time consumed by placer: 35 mins 33 secs 
CPU  time consumed by placer: 35 mins 20 secs 
Writing design to file t1sp.ncd


Total REAL time to Placer completion: 35 mins 40 secs 
Total CPU time to Placer completion: 35 mins 27 secs 

Starting Router

Phase 1: 213945 unrouted;       REAL time: 35 mins 49 secs 

Phase 2: 185919 unrouted;       REAL time: 35 mins 52 secs 

Phase 3: 80092 unrouted;       REAL time: 36 mins 51 secs 

Phase 4: 80092 unrouted; (4572)      REAL time: 37 mins 1 secs 

Phase 5: 80083 unrouted; (0)      REAL time: 37 mins 34 secs 

Phase 6: 80083 unrouted; (0)      REAL time: 37 mins 42 secs 

Phase 7: 0 unrouted; (0)      REAL time: 39 mins 21 secs 

Phase 8: 0 unrouted; (0)      REAL time: 39 mins 53 secs 

Total REAL time to Router completion: 39 mins 55 secs 
Total CPU time to Router completion: 39 mins 41 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                clkm |BUFGCTRL_X0Y30| No   |16979 |  0.969     |  3.548      |
+---------------------+--------------+------+------+------------+-------------+
|         ethi.tx_clk |BUFGCTRL_X0Y31| No   |  111 |  0.216     |  3.280      |
+---------------------+--------------+------+------+------------+-------------+
|         ethi.rx_clk |BUFGCTRL_X0Y24| No   |  102 |  0.238     |  3.285      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

Timing Score: 0

Number of Timing Constraints that were not applied: 8

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "clkgen0/xc2v.v/c | SETUP   |     0.042ns|    28.486ns|       0|           0
  lk0B" derived from  NET "lclk" PERIOD = 2 | HOLD    |     0.316ns|            |       0|           0
  0 ns HIGH 50%                             |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  OFFSET = IN 8 ns BEFORE COMP "etx_clk"    | SETUP   |     1.667ns|     6.333ns|       0|           0
------------------------------------------------------------------------------------------------------
  OFFSET = IN 8 ns BEFORE COMP "erx_clk"    | SETUP   |     1.696ns|     6.304ns|       0|           0
------------------------------------------------------------------------------------------------------
  OFFSET = OUT 15 ns AFTER COMP "etx_clk"   | MAXDELAY|     4.379ns|    10.621ns|       0|           0
------------------------------------------------------------------------------------------------------
  OFFSET = IN 8 ns BEFORE COMP "clk"        | SETUP   |     6.137ns|     1.863ns|       0|           0
------------------------------------------------------------------------------------------------------
  OFFSET = OUT 37 ns AFTER COMP "clk"       | MAXDELAY|    30.244ns|     6.756ns|       0|           0
------------------------------------------------------------------------------------------------------
  NET "eth0.etxc_pad/xcv.x0/tx_clk_c" PERIO | SETUP   |    30.499ns|     9.501ns|       0|           0
  D = 40 ns HIGH 50%                        | HOLD    |     0.497ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  NET "eth0.erxc_pad/xcv.x0/rx_clk_c" PERIO | SETUP   |    33.117ns|     6.883ns|       0|           0
  D = 40 ns HIGH 50%                        | HOLD    |     0.501ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  NET "lclk" PERIOD = 20 ns HIGH 50%        | N/A     |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------
  NET "pci_clk_IBUF" PERIOD = 30 ns HIGH 50 | N/A     |         N/A|         N/A|     N/A|         N/A
  %                                         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_clk = PERIOD TIMEGRP "clk" 20 ns HIGH  | N/A     |         N/A|         N/A|     N/A|         N/A
  50%                                       |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_erx_clk = PERIOD TIMEGRP "erx_clk" 20  | N/A     |         N/A|         N/A|     N/A|         N/A
  ns HIGH 50%                               |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_etx_clk = PERIOD TIMEGRP "etx_clk" 20  | N/A     |         N/A|         N/A|     N/A|         N/A
  ns HIGH 50%                               |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_clkgen0_xc2v_v_clk0B = PERIOD TIMEGRP  | N/A     |         N/A|         N/A|     N/A|         N/A
  "clkgen0_xc2v_v_clk0B" TS_clk / 0.7       |         |            |            |        |            
     HIGH 50%                               |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  OFFSET = OUT 11 ns AFTER COMP "pci_clk"   | N/A     |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------
  OFFSET = IN 7 ns BEFORE COMP "pci_clk"    | N/A     |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 67 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 40 mins 31 secs 
Total CPU time to PAR completion: 40 mins 16 secs 

Peak Memory Usage:  1090 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 74
Number of info messages: 0

Writing design to file t1sp.ncd



PAR done!
trce -v 25 t1sp.ncd t1sp.pcf
Release 9.2.04i - Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.


Loading device for application Rf_Device from file '4vlx100.nph' in environment
/usr/local/xilinx/ise92i01.
   "t1sp" is an NCD, version 3.1, device xc4vlx100, package ff1513, speed -10
The STEPPING level for this design is 0.
WARNING:Timing:3224 - The clock pci_clk associated with OFFSET = OUT 11 ns AFTER
   COMP "pci_clk"; does not clock any registered output components.
WARNING:Timing:3225 - Timing constraint OFFSET = OUT 11 ns AFTER COMP "pci_clk";
   ignored during timing analysis
WARNING:Timing:3224 - The clock pci_clk associated with OFFSET = IN 7 ns BEFORE
   COMP "pci_clk"; does not clock any registered input components.
WARNING:Timing:3225 - Timing constraint OFFSET = IN 7 ns BEFORE COMP "pci_clk";
   ignored during timing analysis
--------------------------------------------------------------------------------
Release 9.2.04i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

trce -v 25 t1sp.ncd t1sp.pcf


Design file:              t1sp.ncd
Physical constraint file: t1sp.pcf
Device,speed:             xc4vlx100,-10 (PRODUCTION 1.68 2007-11-08, STEPPING
level 0)
Report level:             verbose report, limited to 25 items per constraint
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
   50 Ohm transmission line loading model.  For the details of this model, and
   for more information on accounting for different loading conditions, please
   see the device datasheet.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 5610406 paths, 0 nets, and 204282 connections

Design statistics:
   Minimum period:  28.486ns (Maximum frequency:  35.105MHz)
   Minimum input required time before clock:   6.382ns
   Minimum output required time after clock:  10.697ns


Analysis completed Wed Jun 25 13:14:45 2008
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Number of info messages: 2
Total time: 1 mins 40 secs 
bitgen t1sp -d -m -w -f ../../boards/gr-cpci-xc4v/default.ut
Release 9.2.04i - Bitgen J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '4vlx100.nph' in environment
/usr/local/xilinx/ise92i01.
   "t1sp" is an NCD, version 3.1, device xc4vlx100, package ff1513, speed -10
The STEPPING level for this design is 0.
Opened constraints file t1sp.pcf.

Wed Jun 25 13:15:09 2008

Creating bit map...
Saving bit stream in "t1sp.bit".
Creating bit mask...
Saving mask bit stream in "t1sp.msk".
Bitstream generation is complete.
